Abstract: An ESD (electrostatic discharge) protection circuit employs a field oxide region between the drain region and the source region to break a surface channel between the drain region and the source region. As a result, the whole ESD current is discharged via the substrate to the ground by using a gate-modulated field-oxide device, and the potential endurance of ESD device can be improved. Additionally, the invention utilizes circuit technology to detect an ESD signal so that the response speed can be increased. Furthermore, the invention can maintain a deep current path due to the gate-modulated field-oxide device for improving its ESD robustness and decreasing the device size effectively and achieving a better ESD protection efficiency.

Abstract: A novel low-voltage-triggered semiconductor controlled rectified (LVTSCR) as an ESD protection device is provided in this invention. The ESD protection device of the present invention has a lateral SCR (LSCR) structure with two electrodes and a MOS for triggering the LSCR. A dummy gate and a doped region are used to isolate the MOS from one of these two electrodes. The dummy gate is designed to block the formation of field-oxide layer formed in the device structure of the lateral SCR. Therefore, the proposed SCR device has a shorter current path in CMOS process, especially in the CMOS process with shallow trench isolation (STI) field-oxide layer. During an ESD, the current path in the ESD protection device is much shorter, and the turn-on speed and the ESD tolerance level are thereby enhanced.

Abstract: An open drain FET driver circuit at an input-output pad of a semiconductor chip and a frame of the same conductivity type as the drain and source diffusions of the driver is formed around the driver (or partly around the driver). The frame is connected to Vdd and forms the diffusion for the Vdd end of a field FET. The drain of the driver forms the diffusion for the pad end of this field FET and the pad to Vdd FET breaks down in response to an ESD voltage between the pad and Vdd and provides a path for ESD current that the open drain driver itself does not provide. Optionally, a second field FET is formed between the source of the driver FET and the frame and this FET conducts an ESD current between the pad and Vdd in series with the driver. With this cell array structure, the junction capacitance which the ESD protection devices contribute to the pad can be significantly reduced for high speed I/O applications.

Abstract: An electrostatic discharge (ESD) device comprising a field implant region being in the substrate. A STI is on the field implant region and a gate oxide layer is on the STI. A S/D region is below the gate oxide layer and is on the two sides of the STI. A gate is on the gate oxide layer and a spacer is on the sidewall of the gate. Some alternatives can be devised as follows: (1) The length between STI region and LDD region is zero; (2) without LDD region; (3) with an N well region below the field implant region, the LDD region and S/D region; (4) with a deep N well region below the N well region. The ESD device in the present invention has a deeper current path to increase the heat dissipation through a larger device volume. Therefore, the device can sustain a much higher ESD robustness in a smaller silicon area.

Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the fill width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.

Abstract: The invention discloses a method of forming an ESD protection device without adding the extra mask layers into the traditional CMOS process. At first, P-wells, N-wells, and isolations are formed in a semiconductor substrate. Next, an NMOS transistor with a gate dielectric layer, a gate electrode, source/drain regions, lightly doped source/drain regions, and insulator spacers is formed on the substrate. Particularly, N-wells are also formed in a part of the source/drain regions of the NMOS transistor. Thereafter, ESD protection regions are formed under the source/drain regions by performing P+ ESD protection implantation. Such ESD protection device has a low junction breakdown voltage, quick response speed, and a small junction capacitance.

Abstract: The invention discloses a method of forming an ESD protection device without adding the extra mask layers into the traditional CMOS process. At first, P-wells, N-wells, and isolations are formed in a semiconductor substrate. Next, an NMOS transistor with a gate dielectric layer, a gate electrode, source/drain regions, lightly doped source/drain regions, and insulator spacers is formed on the substrate. Particularly, N-wells are also formed in a part of the source/drain regions of the NMOS transistor. Thereafter, ESD protection regions are formed under the source/drain regions by performing P+ ESD protection implantation. Such ESD protection device has a low junction breakdown voltage, quick response speed, and a small junction capacitance.

Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the full width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.

Abstract: In this invention a second gate is created in the area of the drain of a host transistor. The second gate overlies an N-well region and separates the drain of the host transistor into two portions. One portion of the drain is between the field oxide and the second gate and contains the contact for the drain. The second portion of the drain lies between the first gate which controls current in the drain and the second gate. The second gate provides a mask for the siliciding of the drain and provides a high impedance to drain current. In the event of an ESD, drain current is forced down into the N-well through one portion of the drain, under the second gate, and back up through the second portion of the drain providing a longer path and additional bulk material into which to dissipate the energy from an ESD event. Without using an extra mask to block the silicide, the second gate provides a silicide blocking effect to the drain of the ESD protection device.