Abstract: A PLL circuit has an averaging device for averaging a rectangular wave signal output from a phase comparator at every period of a reference clock signal, and for outputting the average value. After the establishment of the phase synchronization of the PLL circuit, the average value of the averaging device becomes a stationary reference level. Accordingly, the output clock signal generated by a voltage controlled oscillator can reduce its output frequency fluctuations in accordance with the reference level.

Abstract: A PLL circuit has an averaging device for averaging a rectangular wave signal output from a phase comparator at every period of a reference clock signal, and for outputting the average value. After the establishment of the phase synchronization of the PLL circuit, the average value of the averaging device becomes a stationary reference level. Accordingly, the output clock signal generated by a voltage controlled oscillator can reduce its output frequency fluctuations in accordance with the reference level.

Abstract: A phase locked loop (PLL) circuit including a phase comparator 2 that compares a phase of a reference clock signal with that of a comparison clock signal to produce a phase comparison signal having three-level outputs of a high voltage (H) level, a low voltage (L) level, and a reference level, and outputs an H or L level signal for duration corresponding to a detected phase difference or outputs a reference level signal when there is no phase difference detected; a level shifter 3 that serves to hold the rectangular waveform of the phase comparison signal from the phase comparator 2; a voltage controlled oscillator (VCO) 4 that advances the phase upon receipt of the H level signal and delay the phase upon receipt of the L level signal; and a frequency divider 5 that divides a frequency of an oscillation clock from the VCO 4 to produce a comparison clock signal.

Abstract: A voice frequency communication apparatus which is capable of detecting and processing the voice frequency terminal signal and non-voice frequency terminal signal and is also capable of realizing communication with ordinary voice frequency terminal signal and non-voice frequency terminal signal without erroneous changeover of the signal processing path because of always monitoring the sending/receiving data with CPU because of providing the constitution to always monitor the sending/receiving data by providing a central control circuit (CPU) having the constitution to always monitor the digital signal output of the detection circuit having the fuction to convert, when the analog input signal is non-voice frequency terminal signal, such non-voice frequency terminal signal into the digital data signal after detecting such signal and to convert, on the contrary, the digital data signal into the analog non-voice frequency terminal signal and the digital data signal to be input from the digital communication line