Patents by Inventor Geoffrey Charles Gardner

Geoffrey Charles Gardner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362487
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. Gronin, Geoffrey Charles Gardner, Raymond Leonard Kallaher
  • Publication number: 20220149262
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: December 23, 2021
    Publication date: May 12, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Patent number: 11211543
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Patent number: 11201273
    Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 14, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Igorevich Pikulin, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Georg Wolfgang Winkler, Sergei Vyatcheslavovich Gronin, Peter Krogstrup Jeppesen, Michael James Manfra, Andrey Antipov, Roman Mykolayovych Lutchyn
  • Publication number: 20210376572
    Abstract: A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Sergei V. GRONIN, Geoffrey Charles GARDNER, Raymond Leonard KALLAHER
  • Publication number: 20210257537
    Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.
    Type: Application
    Filed: April 7, 2021
    Publication date: August 19, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Sergei Vyacheslavovich Gronin, Geoffrey Charles Gardner
  • Publication number: 20210175408
    Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
    Type: Application
    Filed: February 20, 2020
    Publication date: June 10, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey Charles Gardner, Asbjørn Cennet Cliff Drachmann, Charles Masamed Marcus, Michael James Manfra
  • Publication number: 20210126181
    Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Georg Wolfgang Winkler, Roman Mykolayovych Lutchyn, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Sergei Vyatcheslavovich Gronin, Michael James Manfra, Farhad Karimi
  • Patent number: 10978632
    Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Sergei Vyatcheslavovich Gronin, Geoffrey Charles Gardner
  • Publication number: 20210083166
    Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.
    Type: Application
    Filed: September 13, 2019
    Publication date: March 18, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Igorevich Pikulin, Geoffrey Charles Gardner, Raymond Leonard Kallaher, Georg Wolfgang Winkler, Sergei Vyatcheslavovich Gronin, Peter Krogstrup Jeppesen, Michael James Manfra, Andrey Antipov, Roman Mykolayovych Lutchyn
  • Publication number: 20200235275
    Abstract: A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Sergei Vyatcheslavovich Gronin, Geoffrey Charles Gardner
  • Patent number: 10629798
    Abstract: In-situ patterning of semiconductor structures is performed using one or more “shadow walls” in conjunction with an angled deposition beam. A shadow wall protrudes outwardly from the surface of a substrate to define an adjacent shadow region in which deposition is prevented due to the shadow wall inhibiting the passage of the angled deposition beam. Hence, deposition will not occur on a surface portion of a semiconductor structure within the shadow region. Shadow walls can thus be used to achieve selective patterning of semiconductor structures. The shadow walls themselves are formed of semiconductor. In one implementation, the semiconductor structure and the one or more shadow walls used to selectively pattern it may be formed using selective area growth (SAG).
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond Leonard Kallaher, Geoffrey Charles Gardner, Sergei Vyacheslavovich Gronin