Patents by Inventor George C. Feth

George C. Feth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4338622
    Abstract: A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow.
    Type: Grant
    Filed: June 29, 1979
    Date of Patent: July 6, 1982
    Assignee: International Business Machines Corporation
    Inventors: George C. Feth, Tak H. Ning, Denny D. Tang, Siegfried K. Wiedmann, Hwa N. Yu
  • Patent number: 4254428
    Abstract: A Schottky diode structure and self-aligned fabrication method wherein the cathode or ohmic contact is disposed in the center of the anode or Schottky contact and is isolated therefrom by an overlapping layer of insulation. This structure has a reduced area size; it allows the use of only one metal line for both anode contacts and affords a marked advantage of device density. The structure includes a substrate having an n+ sub-diffusion therein, an epitaxial layer over the sub-diffusion which serves as the cathode electrode of the Schottky barrier device, and recessed oxide regions on the substrate for isolation. A heavily doped n+ polysilicon layer is disposed over the epitaxial layer and is used as a source of impurities for the diffusion which makes contact to the Schottky barrier diode. The structure is masked and exposed by conventional photolithographic or electron-beam techniques and is etched down to the epitaxial layer leaving a strip of n+ polysilicon.
    Type: Grant
    Filed: December 28, 1979
    Date of Patent: March 3, 1981
    Assignee: International Business Machines Corporation
    Inventors: George C. Feth, Siegfried K. Wiedmann