Patents by Inventor George D. Papasouliotis

George D. Papasouliotis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9240350
    Abstract: A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: January 19, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Christopher R. Hatem, George D. Papasouliotis
  • Patent number: 9123509
    Abstract: Techniques for plasma processing a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a method comprising introducing a feed gas proximate to a plasma source, where the feed gas may comprise a first and second species, where the first and second species have different ionization energies; providing a multi-level RF power waveform to the plasma source, where the multi-level RF power waveform has at least a first power level during a first pulse duration and a second power level during a second pulse duration, where the second power level may be different from the first power level; ionizing the first species of the feed gas during the first pulse duration; ionizing the second species during the second pulse duration; and providing a bias to the substrate during the first pulse duration.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: September 1, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: George D. Papasouliotis, Kamal Hadidi, Helen L. Maynard, Ludovic Godet, Vikram Singh, Timothy J. Miller, Bernard Lindsay
  • Patent number: 8698106
    Abstract: A method and apparatus are described herein which allow the progression of delamination of a film to be monitored. An interferometer is used to detect the onset and progression of thin film delamination. By projecting one or more wavelengths at a surface, and measuring the reflectance of these projected wavelengths, it is possible to monitor the progression of the delamination process. Testing has shown that different stages of the delamination process produce different reflectance graphs. This information can be used to establish implantation parameters, or can be used as an in situ monitor. The same techniques can be used for other applications. For example, in certain implantation systems, such as PECVD, a film of material may developed on the walls of the chamber. The techniques described herein can be used to monitor this separation, and determine when preventative maintenance may be performed on the chamber.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: April 15, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Helen Maynard, George D. Papasouliotis
  • Patent number: 8679960
    Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: March 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin, Helen L. Maynard, Ludovic Godet
  • Patent number: 8664561
    Abstract: A method is disclosed for adjusting the composition of plasmas used in plasma doping, plasma deposition and plasma etching techniques. The disclosed method enables the plasma composition to be controlled by modifying the energy distribution of the electrons present in the plasma. Energetic electrons are produced in the plasma by accelerating electrons in the plasma using very fast voltage pulses. The pulses are long enough to influence the electrons, but too fast to affect the ions significantly. Collisions between the energetic electrons and the constituents of the plasma result in changes in the plasma composition. The plasma composition can then be optimized to meet the requirements of the specific process being used. This can entail changing the ratio of ion species in the plasma, changing the ratio of ionization to dissociation, or changing the excited state population of the plasma.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: March 4, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kamal Hadidi, Rajesh Dorai, Bernard G. Lindsay, Vikram Singh, George D. Papasouliotis
  • Patent number: 8592783
    Abstract: An improved plasma processing chamber is disclosed, wherein some or all of the components which are exposed to the plasma are made of, or coated with, titanium diborane. Titanium diborane has a hardness in excess of 9 mhos, making it less susceptible to sputtering. In addition, titanium diborane is resistant to fluoride and chlorine ions. Finally, titanium diborane is electrically conductive, and therefore the plasma remains more uniform over time, as charge does not build on the surfaces of the titanium diborane components. This results in improved workpiece processing, with less contaminants and greater uniformity. In other embodiments, titanium diborane may be used to line components within a beam line implanter.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: November 26, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kamal Hadidi, George D. Papasouliotis, Craig R. Chaney
  • Patent number: 8507372
    Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: August 13, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin
  • Publication number: 20130075253
    Abstract: An improved plasma processing chamber is disclosed, wherein some or all of the components which are exposed to the plasma are made of, or coated with, titanium diborane. Titanium diborane has a hardness in excess of 9 mhos, making it less susceptible to sputtering. In addition, titanium diborane is resistant to fluoride and chlorine ions. Finally, titanium diborane is electrically conductive, and therefore the plasma remains more uniform over time, as charge does not build on the surfaces of the titanium diborane components. This results in improved workpiece processing, with less contaminants and greater uniformity. In other embodiments, titanium diborane may be used to line components within a beam line implanter.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 28, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Kamal Hadidi, George D. Papasouliotis, Craig R. Chaney
  • Publication number: 20120309180
    Abstract: A method of forming a retrograde material profile in a substrate includes forming a surface peak profile on the substrate. Ions are then implanted into the substrate to form a retrograde profile from the surface peak profile, at least one of an ion implantation dose and an ion implantation energy of the implanted ions being chosen so that the retrograde profile has a peak concentration that is positioned at a desired distance from the surface of the substrate.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 6, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Ludovic Godet, George D. Papasouliotis
  • Publication number: 20120295444
    Abstract: A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Ludovic Godet, Christopher R. Hatem, George D. Papasouliotis
  • Publication number: 20120295430
    Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 22, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin
  • Publication number: 20120263887
    Abstract: An apparatus for depositing a coating may comprise a first processing chamber configured to deposit a first reactant as a reactant layer on a substrate during a first time period. A second processing chamber may be configured to direct ions incident on the substrate at a second time and configured to deposit a second reactant on the substrate during a second time period, wherein the second reactant is configured to react with the reactant layer.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: George D. Papasouliotis, Ludovic Godet
  • Patent number: 8202792
    Abstract: A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 19, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin
  • Publication number: 20120009798
    Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Helen Maynard, George D. Papasouliotis
  • Publication number: 20110309049
    Abstract: Techniques for plasma processing a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a method comprising introducing a feed gas proximate to a plasma source, where the feed gas may comprise a first and second species, where the first and second species have different ionization energies; providing a multi-level RF power waveform to the plasma source, where the multi-level RF power waveform has at least a first power level during a first pulse duration and a second power level during a second pulse duration, where the second power level may be different from the first power level; ionizing the first species of the feed gas during the first pulse duration; ionizing the second species during the second pulse duration; and providing a bias to the substrate during the first pulse duration.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 22, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: George D. PAPASOULIOTIS, Kamal HADIDI, Helen L. MAYNARD, Ludovic GODET, Vikram SINGH, Timothy J. MILLER, Bernard LINDSAY
  • Patent number: 7927986
    Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
  • Publication number: 20110086501
    Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: George D. Papasouliotis, Vikram Singh, Heyun Yin, Helen L. Maynard, Ludovic Godet
  • Patent number: 7892985
    Abstract: Improved methods for preparing a low-k dielectric material on a substrate using microwave radiation are provided. The use of microwave radiation allows the preparation of low-k films to be accomplished at low temperatures. According to various embodiments, microwave radiation is used to remove porogen from a precursor film and/or to increase the strength of the resulting porous dielectric layer. In a preferred embodiment, methods involve (a) forming a precursor film that contains a porogen and a structure former on a substrate, (b) exposing the precursor film to microwave radiation to remove the porogen from the precursor film to thereby create voids within the dielectric material and form the porous low-k dielectric layer and (c) exposing the dielectric material to microwave radiation in a manner that increases the mechanical strength of the porous low-k dielectric layer.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: February 22, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Seon-Mee Cho, George D. Papasouliotis, Mike Barnes
  • Publication number: 20110039034
    Abstract: A method of depositing and crystallizing materials on a substrate is disclosed. In a particular embodiment, the method may include creating a plasma having deposition-related species and energy-carrying species. During a first time period, no bias voltage is applied to the substrate, and species are deposited on the substrate via plasma deposition. During a second time period, a voltage is applied to the substrate, which attracts ions to and into the deposited species, thereby causing the deposited layer to crystallize. This process can be repeated until an adequate thickness is achieved. In another embodiment, the bias voltage or bias pulse duration can be varied to change the amount of crystallization that occurs. In another embodiment, a dopant may be used to dope the deposited layers.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 17, 2011
    Inventors: Helen Maynard, George D. Papasouliotis, Vikram Singh, Christopher Hatem, Ludovic Godet
  • Publication number: 20110000896
    Abstract: A method is disclosed for adjusting the composition of plasmas used in plasma doping, plasma deposition and plasma etching techniques. The disclosed method enables the plasma composition to be controlled by modifying the energy distribution of the electrons present in the plasma. Energetic electrons are produced in the plasma by accelerating electrons in the plasma using very fast voltage pulses. The pulses are long enough to influence the electrons, but too fast to affect the ions significantly. Collisions between the energetic electrons and the constituents of the plasma result in changes in the plasma composition. The plasma composition can then be optimized to meet the requirements of the specific process being used. This can entail changing the ratio of ion species in the plasma, changing the ratio of ionization to dissociation, or changing the excited state population of the plasma.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 6, 2011
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kamal Hadidi, Rajesh Dorai, Bernard G. Lindsay, Vikram Singh, George D. Papasouliotis