Abstract: In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communication system and is received as a distorted signal that is compared to a known version of the originally transmitted signal. A comparison signal related to the difference between the originally transmitted signal (as represented by the known version of the originally transmitted signal) and the distorted predetermined signal as received at the receiving end is employed to adjust the transfer characteristic of a programmable converter to compensate for the distortion introduced by the communication system.

Abstract: In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communication system and is received as a distorted signal that is compared to a known version of the originally transmitted signal. A comparison signal related to the difference between the originally transmitted signal (as represented by the known version of the originally transmitted signal) and the distorted predetermined signal as received at the receiving end is employed to adjust the transfer characteristic of a programmable converter to compensate for the distortion introduced by the communication system.

Abstract: An integrated circuit which includes a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter employs oppositely coupled comparators and logic circuitry to generate a signal upon a bit determination, with the signal latching the determined bit, resetting the comparators for the subsequent bit determination, and if additional bit(s) are to be determined, commencing the subsequent bit determination. The converter may be configured as a single ended, differential or complimentary circuit.

Abstract: There is disclosed an integrated circuit including a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter can select which of at least two clock signals of different frequency drive the successive approximation converter for each bit determination. Each bit determination may employ a different clock frequency, or a particular clock frequency could be used for multiple bit determinations. The clock signals may be generated within the analog-to-digital converter, or the clock signal may be provided to the analog-to-digital converter.

Abstract: An integrated circuit includes a variable bit-depth successive approximation analog-to-digital converter. The variable bit-depth successive approximation analog-to-digital converter can select from at least two clock signals of different frequencies to drive the variable bit-depth successive approximation converter for each bit depth application. Within each bit-depth application, the converter may employ more than one clock frequency.

Abstract: An integrated circuit includes a converter for converting a signal from one form to another, one of the forms being analog and the other form being digital. The converter includes a voltage gradient having a plurality of MSB taps spaced there-along with the plurality of LSB taps spaced between adjacent MSB taps. An array of comparators are coupled to the voltage gradient with each comparator providing an output. A matrix of switches are coupled between the voltage gradient and the comparator inputs. The first inputs of the comparators in the array are coupled to a sample-and-hold circuit which provides a sample of the analog input signal. Decode and control logic are coupled to comparator outputs to provide a control to the matrix of switches to determine which taps of the voltage gradient are coupled as second inputs to the comparators in the array of comparators and also to provide the resultant output representation of the sampled analog input signal.

Abstract: There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more enhanced majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal.

Abstract: There is disclosed, a converter for converting an input signal from one form to another includes a generator circuit for generating as a thermometer code a plurality of binary signals from the input signal. The converter includes one or more pseudo-majority gate circuits for correcting a broken thermometer code to be a corrected thermometer code. The corrected thermometer code is decoded to provide a digital code corresponding to the input signal. There may be more than one stage of pseudo-majority gate correction.

Abstract: There is disclosed an integrated circuit including a resistor string comprising a plurality of resistors. The resistor string includes a first array of resistors for determining a predetermined number, M, of most significant bits, and a second array of resistors for determining a predetermined number, L, of least significant bits. Each of the first and second arrays of resistors define intermediate taps. First and second arrays of switching transistors are coupled to the respective taps in respective first and second arrays of resistors. Switches in the first array of switching transistors are coupled between a respective intermediate tap in the first array of resistors and a first output node. Transistors in a second array of switching transistors are coupled between a respective intermediate tap in the second array of resistors and a second output node.

Abstract: There is disclosed an integrated circuit in accordance with an illustrative embodiment of the present invention, method of operating a digital converter includes a capacitor on which a sampled analog signal is stored. The capacitor has a first element and a second element. The second element is capable of being referenced to more than one potential. The analog-to-digital converter includes a voltage gradient and a comparator for comparing the sampled analog signal to selected voltages of the voltage gradient to indicate which is larger. Each of the voltages developed along the voltage gradient corresponds to a digital code representative of the voltage.

Abstract: An integrated circuit for converting an analog signal to a digital signal includes a resistor string comprised of a plurality of serially coupled resistors coupled between a high voltage reference and a low voltage reference. Intermediate taps are defined at the junctions of the resistors in the resistor string. At least one comparator has first and second inputs and an output. The first input of the comparator is capable of being selectively coupled to preselected ones of the intermediate taps. The second input is capable of being switched between an unknown analog input in conversion mode and a predetermined tap that provides a nominal voltage at the second input in calibration mode. A selection circuit for sequencing through the preselected ones of the intermediate taps selects one of the preselected ones of the intermediate taps as a selected tap for compensating for the offset of the at least one comparator. The selection circuit stores the selected tap for subsequent use during operation of the circuit.