Patents by Inventor George Frederick Walker

George Frederick Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040084782
    Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said the device chips are joined to said the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
    Type: Application
    Filed: October 23, 2003
    Publication date: May 6, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
  • Patent number: 6661098
    Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
  • Patent number: 6646345
    Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: November 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
  • Publication number: 20030137058
    Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker
  • Publication number: 20030136813
    Abstract: A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Harold Magerlein, Samuel Roy McKnight, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Joseph J. Van Horn, Richard Paul Volant, George Frederick Walker
  • Publication number: 20030136814
    Abstract: A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce Kenneth Furman, Maheswaran Surendra, Sherif A. Goma, Simon M. Karecki, John Harold Magerlein, Kevin Shawn Petrarca, Sampath Purushothaman, Carlos Juan Sambucetti, Richard Paul Volant, George Frederick Walker, Anna Karecki
  • Publication number: 20030048108
    Abstract: The present invention is directed to a structure comprising a substrate having a surface; a plurality of elongated electrical conductors extending away from the surface; each of said elongated electrical conductors having a first end affixed to the surface and a second end projecting away from the surface; there being a plurality of second ends; and a means for positioning and maintaining the plurality of the second ends in substantially fixed positions with respect to each other. The structure is useful as a probe for testing and burning in integrated circuit chips at the wafer level.
    Type: Application
    Filed: May 14, 2002
    Publication date: March 13, 2003
    Inventors: Brian Samuel Beaman, Fuad Elias Doany, Keith Edward Fogel, James Lupton Hedrick, Paul Alfred Lauro, Maurics Heathcote Norcott, John James Ritsko, Sang-Hyon Paek, Leathen Shi, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20020123220
    Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.
    Type: Application
    Filed: September 27, 2001
    Publication date: September 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, George Frederick Walker, John G. Gaudiello, Horatio Seymour Wildman
  • Patent number: 6414509
    Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventors: Anilkumar Chinuprasad Bhatt, Leo Raymond Buda, Robert Douglas Edwards, Paul Joseph Hart, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla, Richard Gerald Murphy, George John Saxenmeyer, Jr., George Frederick Walker, Bette Jaye Whalen, Richard Stuart Zarr
  • Patent number: 6351134
    Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: February 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: James Marc Leas, Robert William Koss, Jody John Van Horn, George Frederick Walker, Charles Hampton Perry, David Lewis Gardell, Steve Leo Dingle, Ronald Prilik
  • Publication number: 20020014004
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed ion the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 7, 2002
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20020011001
    Abstract: A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.
    Type: Application
    Filed: October 10, 2001
    Publication date: January 31, 2002
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice H. Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20020003432
    Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.
    Type: Application
    Filed: May 7, 1999
    Publication date: January 10, 2002
    Inventors: JAMES MARC LEAS, ROBERT WILLIAM KOSS, JODY JOHN VAN HORN, GEORGE FREDERICK WALKER, CHARLES HAMPTON PERRY, DAVID LEWIS GARDELL, STEVE LEO DINGLE, RONALD PRILIK
  • Patent number: 6334247
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Patent number: 6332270
    Abstract: A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice H. Norcott, Da-Yuan Shih, George Frederick Walker
  • Patent number: 6323128
    Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: November 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
  • Publication number: 20010040460
    Abstract: A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.
    Type: Application
    Filed: November 23, 1998
    Publication date: November 15, 2001
    Inventors: BRIAN SAMUEL BEAMAN, KEITH EDWARD FOGEL, PAUL ALFRED LAURO, MAURICE H. NORCOTT, DA-YUAN SHIH, GEORGE FREDERICK WALKER
  • Patent number: 6300780
    Abstract: A high density test probe for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transfer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: October 9, 2001
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Patent number: 6104201
    Abstract: Probe structures for testing electrical interconnections to integrated circuit devices and other electronic components; particularly to testing integrated circuits devices with high density area array solder ball interconnections. The probe structure is formed from a substrated have a surface, with at least one electrical contact location having a perimeter which is raised above the surface, and a location within the boundaries of said perimeter which is raised above the surface.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: August 15, 2000
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Patent number: 6078259
    Abstract: The invention is a radiofrequency identification tag comprising a semiconductor chip having radio frequency, logic, and memory circuits, and an antenna that are mounted on a substrate. The antenna may be used by the chip to modulate an incident RF signal to transfer information to a base station. The antenna comprises one or more lengths of thin wire that are connected directly to the chip by means of wire bonding. The chip and antenna combination are sealed with an organic film covering.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: June 20, 2000
    Assignee: Intermec IP Corp.
    Inventors: Michael John Brady, Thomas Cofino, Harley Kent Heinrich, Glen Walden Johnson, Paul Andrew Moskowitz, George Frederick Walker