Patents by Inventor George Geannopoulos

George Geannopoulos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9696350
    Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Edward A. Burton, Gerhard Schrom, Michael W. Rogers, Alexander Lyakhov, Ravi Sankar Vunnam, Jonathan P. Douglas, Fabrice Paillet, J. Keith Hodgson, William Dawson Kesling, Chiu Keung Tang, Narayanan Raghuraman, Narayanan Natarajan, Samie Samaan, George Geannopoulos
  • Patent number: 7512514
    Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: David Duarte, George Geannopoulos, Usman Mughal, Venkatesh Prasanna, Kedar Mangrulkar, Mathew Nazareth
  • Publication number: 20090079406
    Abstract: A voltage regulator includes an amplifier having first and second outputs, a feedback path coupled between a first input and the first output of the amplifier, and a feed-forward path between the second output of the amplifier and a switch coupled to a reference potential. In operation, a first control signal from the second output of the amplifier is generated based on a comparison of a reference signal and a feedback signal into the first input of the amplifier. The first control signal controls the switch to maintain a substantially constant supply voltage. A second control signal is generated along the feedback path to control controls the amount of supply voltage.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Chaodan Deng, Nasser A. Kurd, George Geannopoulos
  • Publication number: 20080082282
    Abstract: An embodiment of the present invention is a technique for thermal sensing. A sensing structure generates a response according to a local temperature at a first location on a die. A sensor core coupled to the sensing structure via routing lines to provide a measurement of the local temperature from the response. The sensor core is located at a second location remote to the first location and is powered by an analog supply voltage source located in a vicinity of the second location.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: David Duarte, George Geannopoulos, Usman Mughal, Venkatesh Prasanna, Kedar Mangrulkar, Mathew Nazareth
  • Patent number: 6985041
    Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 10, 2006
    Assignee: Intel Corporation
    Inventors: Keng L. Wong, Niraj Bindal, Hong-Piao Ma, George Geannopoulos, Greg F. Taylor, Edward A. Burton
  • Publication number: 20030206067
    Abstract: A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Keng L. Wong, Niraj Bindal, Hong-Piao Ma, George Geannopoulos, Greg F. Taylor, Edward A. Burton
  • Patent number: 6075832
    Abstract: An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: June 13, 2000
    Assignee: Intel Corporation
    Inventors: George Geannopoulos, Keng L. Wong, Greg F. Taylor, Xia Dai
  • Patent number: 4638189
    Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead.
    Type: Grant
    Filed: June 29, 1984
    Date of Patent: January 20, 1987
    Assignee: Monolithic Memories, Incorporated
    Inventors: George Geannopoulos, Cyrus Tsui, Mark Fitzpatrick, Andy Chan