Abstract: A teaching toy (8) includes at least one receptacle (12). Receptacle (12) has a conductive signal-out pad and a plurality of conductive code-in pads (46) at an inner surface. At least one remote unit (14) is included which is removable from receptacle (12). Remote unit (14) has multiple sides and a conductive signal-in pad for capacitive coupling to the signal-out pad. Remote unit (14) also has at least one conductive code-out pad (50) electrically connected to the signal-in pad for capacitive coupling to one of the code-in pads (46). The signal-in pad and the code-out pad (50) are disposed on a first side of unit (14). Remote unit (14) also has a datum disposed on a second side. A processor (20) is included for generating a control signal to the signal-out pad and detecting data signals from the code-in pads (46). Processor (20) associates the data signals with and generates data representing the datum. A memory (22) is included which stores instructions for operating processor (20).

Abstract: An inductive coupled object identification system (FIGS. 2a and 2b) uses inductive coupling to detect and identify objects. Each object includes an object resonance circuit (LT/CT) with a unique object resonance frequency. Base electronics (50) includes an inductive-coupling base coil (L1) coupled to an oscillator circuit (60). To detect an object, the oscillator circuit continually sends START pulses to the base coil. When an object is proximate to the base coil, a START pulse is inductively coupled to the object resonance circuit, causing it to resonate at the object resonance frequency. This resonance condition is detected by the oscillator circuit, which outputs an oscillation signal FREQ at the object resonance frequency. Frequency counting logic (70) is used to determine the object resonance frequency, allowing a microcomputer (80) to identify the object. Two embodiments of the object identification system are described: a dynamic embodiment (FIGS.

Abstract: An electronic hand-held, talking learning aid is disclosed. The learning aid includes a MOS speech synthesizer chip having an active surface area on the order of 45,000 square mils. The disclosed speech synthesizer chip includes a digital lattice filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter and associated timing circuits. The learning aid is also provided with a microprocessor which functions as a controller for controlling the operation of the unit. A small speaker is driven by the digital-to-analog converter on the speech synthesis chip and a keyboard and display device are strobed by the microprocessor controller. Features include modes in which a speech synthesizer recites instructions or questions to the operator who must properly respond.

Abstract: An electronic handheld talking translator including a speech synthesis integrated circuit device. The speech synthesis integrated circuit device includes a digital filter, a voiced/unvoiced excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter, a speaker and associated timing circuits. A non-volatile memory stores digital data representative of the correct spellings of selected words in a foreign language and the model vocal tract control data necessary to control the speech synthesis circuit in a manner to cause the selected words to be audibly pronounced by the translator.

Abstract: A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal.

Abstract: A data processing system has two independent read only memories. Each read only memory (ROM) has an individual associated program counter. Table lookup is accomplished by having an instruction signal pattern output from one ROM conditionally advance the program counter of the other ROM. Upon completion of the output from the first ROM, control is transferred to the second ROM, with the second ROM's program counter containing a predetermined value equivalent to the table lookup value desired, or to a branch word pointing to a value or routine in the second ROM. In the preferred embodiment, the execution of a particular data signal pattern (CALL) in a fast read only memory (said first ROM) causes the program counter for the second ROM (main program counter) to advance one step forward in the program count sequence.

Abstract: A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero.

Abstract: This system includes an LPC parameter speech synthesizer which basically needs ten binary bits for each LPC coefficient. However, external sources are allowed reduced storage and frame rate requirements by encoding the set of LPC coefficients in a data frame with bit-allocation, repeat-bit, and variable-length features. A three-memory system provides transformation: a speech word selected by controller 11 is transformed by a ROM (30) into an address to a ROM (12 or 13) which outputs corresponding speech data in reduced encoded format to a ROM (202) which converts the coded frame of coefficients to uncoded ten-bit coefficients as needed by the speech synthesizer.

Abstract: A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Abstract: A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory.

Abstract: An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.

Abstract: A system and method for driving a multiplexed liquid crystal display (LCD) of duty cycle 1/N is described. The drive system includes M number of segment conductors and N number of drive conductors arranged in a matrix array, the intersection of a drive conductor with a respective segment conductor representing one segment of the display. A signal generator is provided for generating first and second electrical signals having respective first and second predetermined frequencies, the second frequency being substantially greater than the first frequency. A first logic circuit applies the second signal to the drive conductors one-at-a-time in a predetermined sequence and applies the first signal during the remainder of the cycle. Similarly, a second logic circuit responsive to data signals indicative of the information to be displayed applies segment signals representing the ON/OFF states of each segment to the respective segment conductors.

Abstract: A speech synthesis system utilizing a linear predictive filter. Voiced and unvoiced excitations are applied to the filter to produce a digital signal representative of human speech. The voiced excitation is provided by a repeating chirp function stored in memory. The unvoiced excitation consists of two excitation signals of opposite sign, stored in programmable memory and randomly addressed. The programmable storage of unvoiced excitation signals allows gain scaling between voiced and unvoiced excitation to be easily accomplished.

Abstract: A system using a digital filter for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment.

Abstract: A speech synthesis circuit capable of being implemented in an integrated circuit is disclosed. The speech synthesis circuit has an input port for receiving frames of data consisting of speech coefficients, a memory for storing interpolated values of the speech coefficients and an interpolator circuit coupled to the input port and to the memory. A synchronous timing circuit is provided for generating a data frame timing signal, interpolation count timing signals and parameter count timing signals. The rate of the parameter count timing signals is a multiple of the rate of the interpolation count timing signals, which is in turn a multiple of the rate of the data frame timing signal. These signals occur at predetermined times and are generated in the disclosed embodiment by Programmed Logic Arrays (PLA's). The data frame timing signal controls the receipt of a new frame of data at the input port.

Abstract: A system incorporating an integrated circuit device or chip which digitally synthesizes human speech using a linear predictive filter. The linear predictive filter comprises a single filter stage only which contains a single multiplier for selectively multiplying a plurality of coefficients, initiating the multiplication of one coefficient at a time, by using a feedback loop with multiplexing techniques so as to input multiplexed signals to the multiplier--as contrasted to a cascade of filter stages. Thus, the single multiplier of the linear predictive filter is utilized repetitively to provide the calculations required. The system also includes a memory for storage of digital filter coefficients, a controller for selectively accessing the coefficients, and a speaker for generating audible sounds.

Abstract: A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero.

Abstract: An integrated chip microprocessor system has a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on such data, an instruction memory for storing a plurality of instruction words, a program counter for addressing the instruction memory, and an instruction word decoder for decoding instruction words outputted from the instruction memory for controlling the operation of the microprocessor system. The instruction word decoder has a branch decoder system for implementing a two cycle branch logic.

Abstract: A method of communicating Digital Speech Data to a speech synthesis circuit. The data is compressed to on the order of 1000-1200 bits, per second for normal human speech. The speech synthesis circuit utilizes linear predictive coding techniques for producing high quality speech or other sounds.The data is preferably stored in a memory which is coupled to the speech synthesis circuit. The data has variable frame lengths; in the disclosed embodiment, four different frame lengths are described having frame lengths from four bits to forty-nine bits. The memory stores the variable frame length data and communicates the same to the speech synthesis circuit in response to certain control signals.

Abstract: A digital filter of the type which may be used in circuits for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment. In either embodiment, the digital filter may be implemented on a single integrated circuit chip.