Patents by Inventor George R. Deibert

George R. Deibert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5146460
    Abstract: Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: September 8, 1992
    Assignee: International Business Machines
    Inventors: Dennis F. Ackerman, David R. Bender, Salina S. Chu, George R. Deibert, Gary G. Hallock, David E. Lackey, Robert G. Sheldon, Thomas A. Stranko