Patents by Inventor George Samachisa

George Samachisa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9721653
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 1, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tianhong Yan, George Samachisa
  • Patent number: 9672916
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Publication number: 20170004881
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Application
    Filed: September 1, 2016
    Publication date: January 5, 2017
    Inventors: Tianhong Yan, George Samachisa
  • Patent number: 9466790
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 11, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: George Samachisa
  • Publication number: 20160211023
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Patent number: 9330763
    Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 3, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Yanli Zhang, George Samachisa, Johann Alsmeier, Jian Chen
  • Patent number: 9331181
    Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 3, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Donovan Lee, James K. Kai, George Samachisa, Henry Chien, George Matamis, Vinod R. Purayath
  • Publication number: 20160072058
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
    Type: Application
    Filed: November 5, 2015
    Publication date: March 10, 2016
    Inventor: George Samachisa
  • Patent number: 9245629
    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 26, 2016
    Assignee: SANDISK 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
  • Patent number: 9236122
    Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: January 12, 2016
    Assignee: SANDISK 3D LLC
    Inventors: Tianhong Yan, George Samachisa, Tz-yi Liu, Tim Chen, Perumal Ratnam
  • Patent number: 9227456
    Abstract: A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: January 5, 2016
    Assignee: SanDisk 3D LLC
    Inventors: Henry Chien, Yao-Sheng Lee, George Samachisa, Johann Alsmeier
  • Patent number: 9190134
    Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 17, 2015
    Assignee: SANDISK 3D LLC
    Inventor: George Samachisa
  • Patent number: 9165940
    Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 20, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
  • Patent number: 9147439
    Abstract: In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 29, 2015
    Assignee: SANDISK 3D LLC
    Inventors: Raul Adrian Cernea, George Samachisa
  • Patent number: 9064547
    Abstract: A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 23, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Raul Adrian Cernea, Yung-Tin Chen, George Samachisa
  • Patent number: 9047983
    Abstract: Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: June 2, 2015
    Assignee: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, George Samachisa
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Publication number: 20150072488
    Abstract: A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Henry Chien, Johann Alsmeier, George Samachisa, Henry Chin, George Matamis, Yuan Zhang, James Kai, Vinod Purayath, Donovan Lee
  • Patent number: 8958228
    Abstract: A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 17, 2015
    Assignee: Sandisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Publication number: 20150036414
    Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
    Type: Application
    Filed: July 24, 2014
    Publication date: February 5, 2015
    Inventors: Tianhong Yan, George Samachisa, Tz-yi Liu, Tim Chen, Perumal Ratnam