Abstract: A current sensor configured to be employed in an array of current sensors and an array of parallel connected current sensors is disclosed. In one embodiment the current sensors comprise integrated circuit current sensors and a plurality of the current sensors are connected in parallel in a number that is selected to at least accommodate the maximum magnitude of a current to be monitored. When configured in parallel as an array of sensors, at least one of the current sensors of the array of current sensors provides an output signal that represents an average of the currents measured by the plurality of current sensors in the array.

Abstract: A control circuit for a multi-phase converter including an analog front-end circuit for receiving and processing an output voltage and current of the converter circuits and an average output current; a digital circuit for producing an output voltage reference for setting a desired output voltage of the converter; and an error circuit for comparing the output voltage reference and a parameter related to said output voltage and current for generating control signals for controlling the converter circuits, said error circuit including an Analog to Digital Converter circuit, further comprising a digital PWM generation circuit controlled by said Analog to Digital converter circuit for generating digital control signals for controlling the converter circuits.

Abstract: A multiphase converter comprising a plurality of converter circuits, each converter circuit having series connected high and low side switches connected across a voltage bus with a common node provided therebetween, each of the common nodes connected through a respective inductor to an output node of the converter coupled to a load, the high and low side switches each being controlled by a control circuit to provide a desired output voltage at the output node, the control circuit including a first circuit for disabling and enabling at least one phase in response to a condition of the load, the circuit causing the high side switch to be turned on prior to the lower side switch when a disabled phase is enabled.

Abstract: A headroom compensation circuit for a voltage converter for ensuring that there is adequate headroom voltage to enable accurate operation of the current sense amplifier sensing the output current of the converter, the headroom compensation circuit comprising an error amplifier for comparing an output voltage of the converter to a reference voltage to set the converter output voltage; and a circuit for providing a bias current to an input of the error amplifier when a supply voltage to the current sense amplifier within a predefined threshold of the converter output voltage to cause the error amplifier to reduce the converter output voltage thereby to increase the headroom voltage for the current sense amplifier, said headroom voltage being defined as a voltage between the supply voltage to the current sense amplifier and said converter output voltage.

Abstract: A control circuit for use in controlling a phase of a multi-phase voltage converter in accordance with an embodiment of the present invention includes a driver operable to provide a first control signal to a high side switch of a half-bridge of the phase and a second control signal to a low side switch of the half bridge, such that a desired output voltage is provided by the phase, current sensing circuitry operable to detect the output current of the phase, a comparator operable to compare the output current to a threshold current value and a disabling device operable to provide an enable/disable signal to disable the driver when the output current is below the threshold current value.

Abstract: A PWM modulator for generating a PWM control signal for operating transistor switches of a phase of a multi-phase converter including a plurality of ramp generators, each ramp generator receiving a dedicated clock input signal corresponding to a phase of the multi-phase converter and providing a ramp signal starting when the dedicated clock signal is received by the ramp generator, one of the plurality of ramp generators being dedicated to provide the PWM control signal; a plurality of comparators, each comparator associated with a respective ramp generator for terminating the ramp signal when a predefined inequality exists between an error amplifier output of a feedback loop of the multi-phase converter and an output of the associated ramp generator; a plurality of current generator circuits, each current generator circuit associated with a respective ramp generator for providing current to the dedicated ramp generator to control the slope of the ramp signal of the dedicated ramp generator, the dedicated ram

Abstract: A multi-phase converter has a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter. Each switching circuit sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed. A clock circuit provides a plurality of out of phase clock signals to determine when each switching circuit provides the switched voltage to the output node. Each switching circuit is connected across a DC bus voltage. A first error amplifier compares a first signal proportional to the output voltage of the converter at the output node with a second signal comprising a first reference voltage and produces a first error signal. A PWM generator compares the first error signal with a third signal comprising a ramp signal from a ramp signal generator circuit and produces a pulse width modulated signal to control the on-times of a switch of the connected switching circuit.

Abstract: A circuit for preventing inductor saturation during a step-up load transient in a multi-phase converter circuit where phases are turned ON sequentially by a shared clock signal with a fixed phase shift, each phase having high- and low-side switches series connected at a switching node, the circuit including at least one closed loop connected to at least one phase for providing ripple current cancellation in input and output sides of the multi-phase converter circuit; an oscillator circuit for providing a signal to turn ON and OFF the high- and low-side switches of each of the phases of the multi-phase converter circuit; and a detection circuit to detect the transient. The detect circuit includes an error amplifier circuit to receive input signals from an output of the multi-phase converter and to provide an error signal; and a clock oscillator frequency changing circuit receiving the error signal for increasing the clock oscillation frequency when said detection circuit detects a step-up load transient.

Abstract: A circuit for detecting faults in a converter, the converter including a switching stage having high- and low-side series switches connected together at a switching node and fault circuitry for managing a plurality of fault conditions, an input voltage source being provided at one terminal of the high-side switch. The circuit including a gate driver circuit connected to gate terminals of the high- and low-side switches for providing PWM signals to control the switching stage; a comparator circuit for comparing a voltage at the switching node to the input voltage and providing an output signal, the comparator circuit having output, positive and negative terminals; a capacitor connected to the output terminal of the comparator circuit to generate an AC component of the comparator circuit output signal; and a rectifier circuit connected to the capacitor for rectifying the AC component of the comparator circuit output signal and providing a fault-indicating signal to the gate driver circuit.

Abstract: A multi-phase converter comprising a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter and wherein each switching circuit under control of the phase controller sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed; and a main control circuit including a clock circuit for providing a first clock signal to each of the switching circuits and a second lower frequency clock signal to a first of the phase controllers, each phase controller having a delay circuit controlled by the first clock signal to provide a delayed second clock signal for coupling to a next one of the phase controllers and in the case of a last one of the phase controllers, back to the main control circuit, whereby a plurality of sequentially delayed second clock signals is provided, one to each of the remaining phase controllers after the first phase controller to determine wh

Abstract: A multi-phase converter comprising a plurality of switching circuits each providing a switched voltage to an output node of the converter and wherein each switching circuit sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed; a clock circuit for providing a plurality of out of phase clock signals to the switching circuits to determine when each switching circuit provides the switched voltage to the output node; each switching circuit comprising first and second series connected switches connected across a DC voltage bus; further comprising a first circuit comparing a first signal proportional to a difference between the output voltage of the converter at the output node and a first reference voltage with a second signal comprising a ramp signal and for producing a pulse width modulated signal to control the on-times of the switches of the connected switching circuit; further comprising a second circuit comparing the first signal proportio

Abstract: A buck converter for providing an output voltage to a load, including a plurality of output switch arrangements having respective output inductors coupled to an output capacitor, the switch arrangements being controllable to provide phase output currents to the output capacitor; a plurality of phase output arrangements respectively coupled to the output switch arrangements, the phase output arrangements being controllable to set the respective phase output currents supplied by the output switch arrangements; a phase control bus communicatively coupled to each of the phase output arrangements; and a phase control arrangement communicatively coupled to the phase control bus, the phase control arrangement being configured to control the phase output arrangements to set the respective phase output currents so that the output voltage approximates the desired voltage; wherein the phase control arrangement and the phase output arrangements are provided as respective integrated circuits.

Abstract: A multi-phase converter comprising 2N+1 inductors; and 2N+1 switching converters parallel connected and each including a switched node; wherein N is an even integer, a pair of said inductors are coupled and wound about a common core and each said coupled inductor is connected at one pole thereof to a respective switched node and at another pole thereof to an output node, and at least one of said inductors is uncoupled from the other inductors.

Abstract: A multiphase converter comprising a plurality of converter circuits, each converter circuit having series connected high and low side switches connected across a voltage bus with a common node provided therebetween, each of the common nodes connected through a respective inductor to an output node of the converter coupled to a load, the high and low side switches each being controlled by a control circuit to provide a desired output voltage at the output node, the control circuit including a first circuit for disabling and enabling at least one phase in response to a condition of the load, the circuit causing the high side switch to be turned on prior to the lower side switch when a disabled phase is enabled.

Abstract: A PWM modulator for generating a PWM control signal for operating transistor switches of a phase of a multi-phase converter including a plurality of ramp generators, each ramp generator receiving a dedicated clock input signal corresponding to a phase of the multi-phase converter and providing a ramp signal starting when the dedicated clock signal is received by the ramp generator, one of the plurality of ramp generators being dedicated to provide the PWM control signal; a plurality of comparators, each comparator associated with a respective ramp generator for terminating the ramp signal when a predefined inequality exists between an error amplifier output of a feedback loop of the multi-phase converter and an output of the associated ramp generator; a plurality of current generator circuits, each current generator circuit associated with a respective ramp generator for providing current to the dedicated ramp generator to control the slope of the ramp signal of the dedicated ramp generator, the dedicated ram

Abstract: A multi-phase converter has a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter. Each switching circuit sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed. A clock circuit provides a plurality of out of phase clock signals to determine when each switching circuit provides the switched voltage to the output node. Each switching circuit is connected across a DC bus voltage. A first error amplifier compares a first signal proportional to the output voltage of the converter at the output node with a second signal comprising a first reference voltage and produces a first error signal. A PWM generator compares the first error signal with a third signal comprising a ramp signal from a ramp signal generator circuit and produces a pulse width modulated signal to control the on-times of a switch of the connected switching circuit.

Abstract: A multi-phase converter comprising 2N+1 inductors; and 2N+1 switching converters parallel connected and each including a switched node; wherein N is an even integer, a pair of said inductors are coupled and wound about a common core and each said coupled inductor is connected at one pole thereof to a respective switched node and at another pole thereof to an output node, and at least one of said inductors is uncoupled from the other inductors.

Abstract: A pulse width modulation control circuit for providing a pulse width modulation signal in accordance with an embodiment of the present application includes a comparator operable to compare a first input to a second input and to provide the pulse width modulation signal based on the comparison, wherein the first input is an error signal and the second input is a ramp signal, wherein a first portion of the ramp is a decreasing ramp signal having a first slew rate and a second portion of the ramp signal is an increasing ramp signal having a second slew rate.

Abstract: A circuit for detecting faults in at least one converter in a converter system, the at least one converter including a switching stage having high- and low-side switches connected at a switching node and fault circuitry for managing a plurality of fault conditions. The circuit including a gate driver circuit connected to gate terminals of the high- and low-side switches for providing PWM signals to control the switching stage; a comparator circuit for comparing a voltage at the switching node to the input voltage and providing an output signal, the comparator circuit having output, positive and negative terminals; a fourth capacitor connected to the output terminal of the comparator circuit to generate an AC component of the comparator circuit output signal; and a rectifier circuit connected to the fourth capacitor for rectifying the AC component of the comparator circuit and providing a fault-indicating signal to the gate driver.

Abstract: A control circuit for use in controlling a phase of a multi-phase voltage converter in accordance with an embodiment of the present invention includes a driver operable to provide a first control signal to a high side switch of a half-bridge of the phase and a second control signal to a low side switch of the half bridge, such that a desired output voltage is provided by the phase, current sensing circuitry operable to detect the output current of the phase, a comparator operable to compare the output current to a threshold current value and a disabling device operable to provide an enable/disable signal to disable the driver when the output current is below the threshold current value.