Patents by Inventor George W. Conner

George W. Conner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9791511
    Abstract: According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system may include a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 17, 2017
    Assignee: Teradyne, Inc.
    Inventors: Thien D. Nguyen, George W. Conner
  • Patent number: 9577818
    Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: February 21, 2017
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Publication number: 20160227004
    Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 4, 2016
    Applicant: Teradyne, Inc.
    Inventor: George W. Conner
  • Publication number: 20140278177
    Abstract: According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system comprises a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Teradyne, Inc.
    Inventors: Thien D. Nguyen, George W. Conner
  • Patent number: 8805636
    Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 12, 2014
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Patent number: 8725489
    Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 13, 2014
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Patent number: 8521465
    Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: August 27, 2013
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Patent number: 8269520
    Abstract: A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: September 18, 2012
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Publication number: 20120221285
    Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.
    Type: Application
    Filed: May 4, 2012
    Publication date: August 30, 2012
    Applicant: Teradyne, Inc.
    Inventor: George W. Conner
  • Patent number: 8195419
    Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: June 5, 2012
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Patent number: 8094766
    Abstract: A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 10, 2012
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Publication number: 20110087942
    Abstract: A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.
    Type: Application
    Filed: October 8, 2009
    Publication date: April 14, 2011
    Applicant: TERADYNE, INC.
    Inventor: George W. Conner
  • Publication number: 20100312516
    Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.
    Type: Application
    Filed: October 30, 2008
    Publication date: December 9, 2010
    Applicant: TERADYNE, INC.
    Inventor: George W. Conner
  • Publication number: 20100313071
    Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.
    Type: Application
    Filed: October 30, 2008
    Publication date: December 9, 2010
    Applicant: Teradyne INc.
    Inventor: George W. Conner
  • Publication number: 20100235135
    Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 16, 2010
    Inventor: George W. Conner
  • Patent number: 7673199
    Abstract: Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: March 2, 2010
    Assignee: Teradyne, Inc.
    Inventors: Peter A. Reichert, Craig E. Robertson, George W. Conner
  • Publication number: 20100002819
    Abstract: A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Inventor: George W. Conner
  • Patent number: 7593497
    Abstract: A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: September 22, 2009
    Assignee: Teradyne, Inc.
    Inventor: George W. Conner
  • Publication number: 20090112548
    Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventor: George W. Conner
  • Publication number: 20090113245
    Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventor: George W. Conner