Patents by Inventor George W. Cox

George W. Cox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4402046
    Abstract: A communication mechanism for use in a multi-processing system wherein several processors share a common memory. Each processor has associated with it a local communication segment, stored in memory. The local communication segment is for processor-specific communication. Another segment, the global communication segment, is common to all processors, and is for system-wide communication. Each communication segment has a field containing control flags. The flags are set by one processor and later inspected by the same or another processor. The inspecting processor is instructed to perform a number of functions specified by the state of the control flags. A count field and a lock field are provided in all communication segments to interlock access to the communication mechanism. A status field is provided in the local communication segments.
    Type: Grant
    Filed: August 5, 1981
    Date of Patent: August 30, 1983
    Assignee: Intel Corporation
    Inventors: George W. Cox, Justin R. Rattner
  • Patent number: 4387427
    Abstract: A general-purpose, tightly-coupled multiprocessing system wherein processors share a common memory. A hardware-recognizable object (a process object) in memory stores access descriptors for controlling the type and extent of access to objects associated with a process, including one describing a buffered port. Another hardware-recognizable object (a processor object) associated with an executing process, stores access descriptors for controlling the type and extent of access to objects associated with a processor, including one describing a dispatching port. Task-dispatching functions are accomplished by hardware-controlled queuing mechanisms at the buffered ports and dispatching ports. These mechanisms allow different processes to communicate with each other and bind ready-to-run processes with available processors for execution.
    Type: Grant
    Filed: October 16, 1980
    Date of Patent: June 7, 1983
    Assignee: Intel Corporation
    Inventors: George W. Cox, Justin R. Rattner
  • Patent number: 4325120
    Abstract: A data processor architecture wherein the processors recognize two basic types of objects, an object being a representation of related information maintained in a contiguously-addresed set of memory locations. The first type of object contains ordinary data, such as characters, integers, reals, etc. The second type of object contains a list of access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. The processors recognize complex objects that are combinations of objects of the basic types. One such complex object (a context) defines an environment for execution of objects accessible to a given instance of a procedural operation. The dispatching of tasks to the processors is accomplished by hardware-controlled queuing mechanisms (dispatching-port objects) which allow multiple sets of processors to serve multiple, but independent sets of tasks.
    Type: Grant
    Filed: December 21, 1978
    Date of Patent: April 13, 1982
    Assignee: Intel Corporation
    Inventors: Stephen R. Colley, George W. Cox, Justin R. Rattner, Roger C. Swanson
  • Patent number: 4315310
    Abstract: An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.
    Type: Grant
    Filed: September 28, 1979
    Date of Patent: February 9, 1982
    Assignee: Intel Corporation
    Inventors: John A. Bayliss, George W. Cox, Bert E. Forbes, Kevin C. Kahn