Patents by Inventor George Z. N. Cai

George Z. N. Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6216219
    Abstract: A microprocessor (12) comprising a memory system (20) for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address. The microprocessor further includes a load target circuit (56 or 112), which comprises a first plurality of entries (116) of a first length and a second plurality of entries (114) of a second length. Each of the first plurality of entries comprises a value (ADDRESS TAG) for corresponding the entry to a corresponding first plurality of data fetching instructions. Further, each of the first plurality of entries further comprises a value (POINTER A) for indicating a corresponding predicted target data address. Each of the second plurality of entries also comprises a value (ADDRESS TAG) for corresponding each of the second plurality of entries to a corresponding second plurality of data fetching instructions.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: April 10, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: George Z. N. Cai, Jonathan H. Shiell
  • Patent number: 6108775
    Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: August 22, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan H. Shiell, George Z. N. Cai
  • Patent number: 6029228
    Abstract: A method of operating a microprocessor (12). The method first receives (64) a plurality of instructions arranged in a sequence from a first instruction through a last instruction. The method second identifies (66) a branch instruction as one of the plurality of instructions, wherein the branch instruction has a target instruction address. The method third determines two factors for the branch instruction, the first being a prediction value (72) indicating whether or not program flow should pass to the target instruction address, and the second being an accuracy measure (74, 76) indicating accuracy of past ones of the prediction value. The method fourth identifies a data fetching instruction following the branch instruction in the plurality of instructions. Lastly, the method issues a prefetch request (70, 78) for the data fetching instruction in response to the accuracy measure.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: February 22, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: George Z. N. Cai, Jonathan H. Shiell
  • Patent number: 5953512
    Abstract: A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: September 14, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: George Z. N. Cai, Jonathan H. Shiell
  • Patent number: 5935241
    Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: August 10, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan H. Shiell, George Z. N. Cai
  • Patent number: 5909566
    Abstract: A method of operating a microprocessor (12) having an on-chip storage resource (100a). The method first receives a data fetching instruction into an instruction pipeline (38) at a first time. The instruction pipeline has a preliminary stage (40), a plurality of stages (42 through 46) following the preliminary stage, and an execution stage (48) following the plurality of stages. The step of receiving a data fetching instruction at the first time comprises receiving the data fetching instruction in the preliminary stage. The method second performs various steps, including fetching a first data quantity (MRU TARGET DATA) for the data fetching instruction to complete the execution stage of the pipeline, completing the execution stage in connection with the data fetching instruction using the first data quantity, and storing the first data quantity in the on-chip storage resource. The method third receives the data fetching instruction into the preliminary stage at a second time (108).
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: June 1, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: George Z. N. Cai, Jonathan H. Shiell