Patents by Inventor Georgios Makris

Georgios Makris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210141989
    Abstract: A method can be executed by at least one processor of a computer to generate synthetic Integrated Circuit (IC) layout patterns, where the method can optionally include accessing attribute values of the IC layout pattern features generated using IC layout patterns from at least one at least one previous generation semiconductor fabrication technology node.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Gaurav Rajavendra Reddy, Mohammad M. Bidmeshki, Georgios Makris
  • Publication number: 20210083673
    Abstract: Illustrative embodiments provide a mixed programmable and application-specific integrated circuit, a method of using the mixed programmable and application-specific integrated circuit and a method of making the mixed programmable and application-specific integrated circuit. The mixed programmable and application-specific integrated circuit includes at least a portion of a programmable transistor array that is programed after fabrication. The programmable transistor array can include at least another portion that is mask programed during fabrication.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Carl Sechen, Georgios Makris, Thomas Broadfoot
  • Patent number: 10855285
    Abstract: Illustrative embodiments provide a field-programmable transistor array and a method of making an integrated circuit comprising a field-programmable transistor array. The field-programmable transistor array comprises a plurality of logic cells. Each of the plurality of logic cells comprises a plurality of columns of transistors. Each of the plurality of columns of transistors comprises a plurality of first transistors and a plurality of second transistors. Each of the plurality of first transistors are individually programmable to be either always on, always off, or to be controlled by a logic signal to be on or off. Each of the plurality of second transistors are configured to be programmed to be always on or always off.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Carl Sechen, Georgios Makris, Gaurav Rajavendra Reddy, Jingxiang Tian
  • Publication number: 20200067511
    Abstract: Illustrative embodiments provide a field-programmable transistor array and a method of making an integrated circuit comprising a field-programmable transistor array. The field-programmable transistor array comprises a plurality of logic cells. Each of the plurality of logic cells comprises a plurality of columns of transistors. Each of the plurality of columns of transistors comprises a plurality of first transistors and a plurality of second transistors. Each of the plurality of first transistors are individually programmable to be either always on, always off, or to be controlled by a logic signal to be on or off. Each of the plurality of second transistors are configured to be programmed to be always on or always off.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Carl Sechen, Georgios Makris, Gaurav Rajavendra Reddy, Jingxiang Tian
  • Patent number: 10511308
    Abstract: Illustrative embodiments provide a field-programmable transistor array and a method of making an integrated circuit comprising a field-programmable transistor array. The field-programmable transistor array comprises a plurality of logic cells. Each of the plurality of logic cells comprises a plurality of columns of transistors. Each of the plurality of columns of transistors comprises a plurality of first transistors and a plurality of second transistors. Each of the plurality of first transistors are individually programmable to be either always on, always off, or to be controlled by a logic signal to be on or off. Each of the plurality of second transistors are configured to be programmed to be always on or always off.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 17, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Carl Sechen, Georgios Makris, Gaurav Rajavendra Reddy, Jingxiang Tian
  • Publication number: 20190103873
    Abstract: Illustrative embodiments provide a field-programmable transistor array and a method of making an integrated circuit comprising a field-programmable transistor array. The field-programmable transistor array comprises a plurality of logic cells. Each of the plurality of logic cells comprises a plurality of columns of transistors. Each of the plurality of columns of transistors comprises a plurality of first transistors and a plurality of second transistors. Each of the plurality of first transistors are individually programmable to be either always on, always off, or to be controlled by a logic signal to be on or off. Each of the plurality of second transistors are configured to be programmed to be always on or always off.
    Type: Application
    Filed: March 27, 2018
    Publication date: April 4, 2019
    Inventors: Carl Sechen, Georgios Makris, Gaurav Rajavendra Reddy, Jingxiang Tian