Abstract: A method of manufacturing a light plate includes defining a three-dimensional model of the light plate. The model includes a translucency map configured to light balance the light plate. The translucency map defines a first portion having a first translucency. The method includes providing the model to an additive layer device; selecting at least one material based on the model; and depositing the at least one material in a layer based on the model. The method includes at least one of adhering the at least two layers of material with one another and cross-linking the at least two layers of material with one another to form a first region of the light plate corresponding to the first portion of the translucency map.

Abstract: An electronic component includes a base insulative layer having first and second surfaces; an electronic device having first and second surfaces; at least one I/O contact located on the first surface of the electronic device; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; a first metal layer disposed on the I/O contact; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer, and located adjacent to the first metal layer. The base insulative layer secures to the electronic device through the first metal layer and removable layer. The first metal layer and removable layer can release the base insulative layer from the electronic device when the first metal layer and removable layer are exposed to a temperature higher than their softening points or melting points.

Abstract: A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.

Abstract: An electromechanical switching system includes a first conductive portion and a second conductive portion. The first conductive portion includes a conductive stationary end and a conductive floating end, connected by a shape memory alloy (SMA). When an input stimulus current is applied to the SMA, changes in the SMA urge motion of the conductive floating end of the first conductive portion toward the second conductive portion, which in turn causes a change in the state of the electromechanical switching system. The input stimulus current may be calculated to satisfy a given response time requirement.

Abstract: A cooling device includes a ceramic substrate with a metal layer bonded to an outer planar surface. The cooling device also includes a channel layer bonded to an opposite side of the ceramic substrate and a manifold layer bonded to an outer surface of the channel layer. The substrate layers are bonded together using a high temperature process such as brazing to form a single substrate assembly. A plenum housing is bonded to the single substrate assembly via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports.

Abstract: A method for forming a tileable detector array is presented.

Abstract: A method for forming a sensor stack is presented. The method includes providing a substrate having a first side and a second side. Furthermore, the method includes disposing an integrated circuit having a first side and a second side on the first side of the substrate, where the integrated circuit comprises a first plurality of contact pads disposed on the first side of the integrated circuit. The method also includes providing a sensor array having a plurality of sensor elements, wherein each of the sensor elements has a first side and a second side, and wherein the sensor array comprises a second plurality of contact pads disposed on the second side of the sensor array.

Abstract: An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a sur

Abstract: A modular and tileable sensor array with routing in the interposer carrying the signals from the sensors to the integrated circuits. In one embodiment a large area modular sensor array assembly includes one or more tileable modules coupled together. The tileable modules have a plurality of transducer cells forming a sensor, an interposer coupled on a first side to the plurality of transducer cells by a plurality, one or more integrated circuits coupled to a second side of the interposer, wherein the interposer is configured to form the connection of at least some of the transducer cells to the integrated circuits, and one or more input/output connectors coupled to the interposer and providing an external interface.

Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

Abstract: An actuator includes a shape memory element formed from a shape memory alloy. The shape memory element is configured such that the actuator is actuated by a change in shape of the shape memory element. The shape memory element may be maintained in a pre-actuated state that is advanced from its rest state, but which is not at its actuated state.

Abstract: A method for forming a sensor stack is presented. The method includes providing a substrate having a first side and a second side. Furthermore, the method includes disposing an integrated circuit having a first side and a second side on the first side of the substrate, where the integrated circuit comprises a first plurality of contact pads disposed on the first side of the integrated circuit. The method also includes providing a sensor array having a plurality of sensor elements, wherein each of the sensor elements has a first side and a second side, and wherein the sensor array comprises a second plurality of contact pads disposed on the second side of the sensor array.

Abstract: A method for forming a tileable detector array is presented.

Abstract: An electronic assembly is provided. The assembly comprises a substrate having a plurality of conductive contacts disposed on a surface of the substrate. The substrate comprises a dielectric material. The assembly comprises a detector having a plurality of conductive contacts disposed on a surface of the detector which is adjacent to the surface of the substrate. At least one compliant interconnect is disposed between the substrate and the detector. The conductive contacts of the substrate and the conductive contacts of the detector are in electrical communication with the compliant interconnect via a conductive epoxy. The compliant interconnect comprises a polymer core having an electrically conductive outer surface. In certain embodiments, the assembly comprises an interposer. In certain embodiments, an under-fill is disposed between the surface of the substrate and the surface of the detector.

Abstract: An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a sur

Abstract: A shape memory element (a structure formed from a shape memory alloy) includes an electrically conductive ferromagnetic material. The ferromagnetic material may be magnetostrictive. In some embodiments, the shape memory element is formed from a shape memory alloy core and has a cladding over the core that includes the ferromagnetic material. In other embodiments, the shape memory alloy may be selected to be ferromagnetic.

Abstract: A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

Abstract: An electrical switching device employs an actuator mechanism formed of a shape memory alloy (SMA). The electrical switching device includes a housing, at least one non-actuated electrical contact supported in the housing, and an actuator assembly contained within the housing. The actuator assembly includes a movable contact for engaging the non-actuated electrical contact and an actuator formed of a shape memory alloy (SMA). Application of a first electrical current to the actuator causes the actuator to move the movable contact to either engage or disengage the non-actuated electrical contact.

Abstract: A modular and tileable sensor array with routing in the interposer carrying the signals from the sensors to the integrated circuits. In one embodiment a large area modular sensor array assembly includes one or more tileable modules coupled together. The tileable modules have a plurality of transducer cells forming a sensor, an interposer coupled on a first side to the plurality of transducer cells by a plurality, one or more integrated circuits coupled to a second side of the interposer, wherein the interposer is configured to form the connection of at least some of the transducer cells to the integrated circuits, and one or more input/output connectors coupled to the interposer and providing an external interface.

Abstract: An ultrasonic monitoring system is formed with a probe unit. In one example an array of transducer cells is arranged in rows and columns formed along a first plane with a first pitch along a first direction. An integrated circuit including an array of circuit cells is formed along a second plane parallel to the first plane. The circuit cells are spaced apart along the first direction at a second pitch smaller than the first pitch. A first of the transducer cells is vertically aligned, along a direction normal to one of the planes, with a first of the circuit cells and having a connection thereto. A second of the transducer cells is offset from vertical alignment with respect to the position of a second circuit cell so as to not overlie the second circuit cell.