Patents by Inventor Gerard Chauvel
Gerard Chauvel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8782675Abstract: A method and system of accessing display window memory. At least some of the illustrative embodiments are methods comprising abstracting display window memory by way of a first software object, accessing the display window memory by routines of a graphics library executed on a first processor (the accessing by way of the first software object), and displaying a window on a display screen, contents of the window selected at least in part by the routines of the graphics library.Type: GrantFiled: November 17, 2006Date of Patent: July 15, 2014Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Gilbert Cabillic
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Patent number: 8539159Abstract: Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.Type: GrantFiled: July 31, 2003Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno
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Patent number: 8516496Abstract: An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.Type: GrantFiled: July 21, 2005Date of Patent: August 20, 2013Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Gerard Chauvel
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Patent number: 8516502Abstract: A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).Type: GrantFiled: April 27, 2007Date of Patent: August 20, 2013Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Gilbert Cabillic, Jean-Philippe Lesot
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Patent number: 8489860Abstract: A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.Type: GrantFiled: December 22, 1997Date of Patent: July 16, 2013Assignee: Texas Instruments IncorporatedInventors: Michael McMahon, Marion C. Lineberry, Matthew A. Woolsey, Gerard Chauvel
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Patent number: 8429383Abstract: A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.Type: GrantFiled: July 31, 2003Date of Patent: April 23, 2013Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Maija Kuusela, Dominique D'Inverno
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Patent number: 8190861Abstract: A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.Type: GrantFiled: February 21, 2007Date of Patent: May 29, 2012Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Gilbert Cabillic, Jean-Philippe Lesot, Dominique D'Inverno, Eric Badi, Serge Lasserre
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Patent number: 8185666Abstract: A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.Type: GrantFiled: April 28, 2005Date of Patent: May 22, 2012Assignee: Texas Instruments IncorporatedInventor: Gerard Chauvel
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Patent number: 8078842Abstract: An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.Type: GrantFiled: July 21, 2005Date of Patent: December 13, 2011Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Gerard Chauvel, Jean-Philippe Lesot
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Patent number: 8046748Abstract: A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.Type: GrantFiled: July 25, 2005Date of Patent: October 25, 2011Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Gerard Chauvel
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Patent number: 8032891Abstract: A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.Type: GrantFiled: May 20, 2002Date of Patent: October 4, 2011Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Dominique D'Inverno, Serge Lasserre, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Frédéric Parain, Jean-Paul Routeau, Salam Majoul
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Patent number: 8024554Abstract: A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction. If the bit is in a second state, both the group and the particular fetched instruction are executed.Type: GrantFiled: July 25, 2005Date of Patent: September 20, 2011Assignee: Texas Instruments IncorporatedInventor: Gerard Chauvel
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Patent number: 7941790Abstract: A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.Type: GrantFiled: October 24, 2001Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Michel Banatre, Gerard Chauvel, Dominique D'Inverno, Teresa Higuera, Valerie Issarny, Serge Lasserre, Frederic Parain, Jean-Paul Routeau
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Patent number: 7930689Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.Type: GrantFiled: July 21, 2005Date of Patent: April 19, 2011Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Gerard Chauvel
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Patent number: 7840784Abstract: A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack.Type: GrantFiled: July 31, 2003Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno
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Patent number: 7840782Abstract: A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.Type: GrantFiled: July 31, 2003Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno
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Patent number: 7757223Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.Type: GrantFiled: July 25, 2005Date of Patent: July 13, 2010Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Mikael Peltier, Gerard Chauvel
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Patent number: 7757067Abstract: A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.Type: GrantFiled: July 31, 2003Date of Patent: July 13, 2010Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Maija Kuusela
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Patent number: 7743384Abstract: A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class defines a handler method for an interrupt and an execution flow execution method that overrides the execution flow execution method of the execution flow class. An interrupt handler object is instantiated using the interrupt handler class, the constructor creates an execution flow context for the handler method, and when the interrupt is signaled, the JVM invokes a native execution flow activation method in the execution flow scheduler to switch to the handler execution flow context and the execution flow execution method to initiate execution of the handler method.Type: GrantFiled: July 26, 2005Date of Patent: June 22, 2010Assignee: Texas Instruments IncorporatedInventors: Gilbert Cabillic, Jean-Philippe Lesot, Gerard Chauvel
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Patent number: 7716673Abstract: A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).Type: GrantFiled: July 31, 2003Date of Patent: May 11, 2010Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Dominique D'Inverno