Patents by Inventor Gerben Willem De Jong

Gerben Willem De Jong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240022216
    Abstract: An analog amplitude pre-distortion circuit and method. The circuit includes a Radio Frequency, RF, input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input for receiving the RF signal from the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a detector stage for detecting an amplitude of the RF signal, and for producing a correction signal based on the amplitude of the RF signal. The bias circuit also includes a bias application stage coupled to the amplifier stage input.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 18, 2024
    Inventors: Gerben Willem de Jong, Jozef Reinerus Maria Bergervoet, Mark Pieter van der Heijden, Bilal Elkassir
  • Publication number: 20240022218
    Abstract: An analog amplitude pre-distortion circuit and method. The circuit includes an RF input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input coupled to the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a transistor having a first current terminal, a second current terminal and a control terminal, wherein the first current terminal is coupled to the amplifier stage input and wherein the second current terminal is coupled to a reference potential. The bias circuit also includes a resistor coupled between the amplifier stage input and the control terminal. The bias circuit also includes a variable reactance component coupled to the control terminal. The bias circuit further includes a capacitor coupled between the control terminal and the reference potential.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 18, 2024
    Inventors: Gerben Willem de Jong, Jozef Reinerus Maria Bergervoet, Mark Pieter van der Heijden
  • Publication number: 20230170853
    Abstract: A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.
    Type: Application
    Filed: November 7, 2022
    Publication date: June 1, 2023
    Inventors: Gian Hoogzaad, Gerben Willem de Jong, Robert Victor Buytenhuijs
  • Patent number: 11482974
    Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 25, 2022
    Assignee: NXP B.V.
    Inventors: Gerben Willem de Jong, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet
  • Publication number: 20210126597
    Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 29, 2021
    Inventors: Gerben Willem de Jong, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet
  • Patent number: 10985795
    Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 20, 2021
    Assignee: NXP B.V.
    Inventors: Xin Yang, Mark Pieter van der Heijden, Gerben Willem de Jong
  • Publication number: 20200274575
    Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided,
    Type: Application
    Filed: February 19, 2020
    Publication date: August 27, 2020
    Inventors: Xin Yang, Mark Pieter van der Heijden, Gerben Willem de Jong
  • Patent number: 10673388
    Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 2, 2020
    Assignee: NXP B.V.
    Inventors: Mark Pieter Van Der Heijden, Gerben Willem De Jong, Xin Yang
  • Publication number: 20190173432
    Abstract: A bias circuit for a bipolar RF amplifier is described. The bias circuit includes a current source coupled to a bias network. The bias network supplies a base current to the transistors in the amplifier circuit of the bipolar RF amplifier. The bias circuit includes a buffer coupled to the bias network and to the bipolar RF amplifier. The buffer provides additional base current to the amplifier circuit of bipolar RF amplifier and sinks avalanche current generated by the amplifier circuit of the bipolar RF amplifier.
    Type: Application
    Filed: September 14, 2018
    Publication date: June 6, 2019
    Inventors: Mark Pieter Van Der Heijden, Gerben Willem De Jong, Xin Yang
  • Patent number: 10090295
    Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 2, 2018
    Assignee: NXP B.V.
    Inventors: Jozef Reinerus Maria Bergervoet, Gerben Willem de Jong, Gian Hoogzaad
  • Patent number: 10050588
    Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 14, 2018
    Assignee: NXP B.V.
    Inventors: Gerben Willem de Jong, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet, Tony Vanhoucke, Gian Hoogzaad, Ivan Matkov Zahariev
  • Publication number: 20180006611
    Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.
    Type: Application
    Filed: May 16, 2017
    Publication date: January 4, 2018
    Inventors: Gerben Willem de Jong, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet, Tony Vanhoucke, Gian Hoogzaad, Ivan Matkov Zahariev
  • Publication number: 20180006021
    Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
    Type: Application
    Filed: June 12, 2017
    Publication date: January 4, 2018
    Inventors: Jozef Reinerus Maria Bergervoet, Gerben Willem de Jong, Gian Hoogzaad
  • Patent number: 8805309
    Abstract: A down-converter for receiving a multiband radio frequency signal (RF) and a local oscillator signal comprises a frequency divider and a heterodyne receive chain. The frequency divider is configured to divide the local oscillator signal and provide different divided local oscillator signals. The heterodyne receive chain comprises a first stage mixer and second stage mixers. The first stage mixer is configured to mix the multiband radio frequency signal and either the local oscillator signal or a divided local oscillator signal to generate a first intermediate frequency signal. Each second stage mixer is configured to mix the first intermediate signal and a divided local oscillator signal to generate second intermediate frequency signals that each represent a band from the multiband radio frequency signal. The frequency divider is configured to provide a different divided local oscillator signal to each of the second stage mixers.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: August 12, 2014
    Assignee: NXP, B.V.
    Inventors: Dominicus Martinus Wilhelmus Leenaerts, Gerben Willem De Jong, Edwin Van Der Heijden, Marcellinus Johannes Maria Geurts
  • Patent number: 8686779
    Abstract: The invention concerns in general measurement of the transfer function of linear time invariant systems, more particular the calibration of such systems based on a measured transfer function. According to a first aspect the present invention an arrangement for measuring the transfer function of a linear time-invariant system is disclosed. According to a second aspect of the present invention the arrangement is implemented into a linear time-invariant circuitry having a transfer function representing the amplitude and phase characteristic of the circuitry, where by means of the arrangement for measuring the transfer function the transfer function can be optimized in accordance with certain criteria on-the-fly, i.e. in or before operation of the circuit. Finally, an effective and simple method for measuring of the transfer function of a linear time-invariant system together with the use or application of the method is shown.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventors: Dennis Jeurissen, Gerben Willem De Jong, Jan Van Sinderen
  • Patent number: 8660508
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 25, 2014
    Assignee: NXP, B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans
  • Publication number: 20130028352
    Abstract: A down-converter for receiving a multiband radio frequency signal (RF) and a local oscillator signal comprises a frequency divider and a heterodyne receive chain. The frequency divider is configured to divide the local oscillator signal and provide different divided local oscillator signals. The heterodyne receive chain comprises a first stage mixer and second stage mixers. The first stage mixer is configured to mix the multiband radio frequency signal and either the local oscillator signal or a divided local oscillator signal to generate a first intermediate frequency signal. Each second stage mixer is configured to mix the first intermediate signal and a divided local oscillator signal to generate second intermediate frequency signals that each represent a band from the multiband radio frequency signal. The frequency divider is configured to provide a different divided local oscillator signal to each of the second stage mixers.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 31, 2013
    Applicant: NXP B.V.
    Inventors: Dominicus Martinus Wilhelmus LEENAERTS, Gerben Willem DE JONG, Edwin VAN DER HEIJDEN, Marcellinus Johannes Maria GEURTS
  • Publication number: 20120154050
    Abstract: A circuit has a reference source (12) for supplying a bias signal to set a small signal transconductance of an amplifier transistor in an amplifier (10) to a predetermined value. The reference source has at least one reference transistor (120a-b, 30). A feedback circuit (128, 129, 38) has an input coupled to the main current channel of the reference transistor or reference transistors (120a-b, 30) and an output coupled to the control electrode of the reference transistor or reference transistors (120a-b, 30). The feedback circuit controls a control voltage at the control electrode, so as to equalize an offset current and a difference between main currents flowing through the current channel of the reference transistor or reference transistors (120a-b, 30), obtained with and without a small voltage offset added to the control voltage.
    Type: Application
    Filed: August 19, 2009
    Publication date: June 21, 2012
    Applicant: NXP B.V.
    Inventor: Gerben Willem De Jong
  • Patent number: 8203375
    Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: June 19, 2012
    Assignee: NXP B.V.
    Inventors: Gerben Willem de Jong, Johannes Hubertus Antonius Brekelmans
  • Publication number: 20120105128
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Application
    Filed: April 23, 2010
    Publication date: May 3, 2012
    Applicant: NXP B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans