Patents by Inventor Gheorghe Stefan
Gheorghe Stefan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9563433Abstract: The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a bus and is able to send an instruction to the array of processing elements. The processing elements are separated into classes and only execute instructions that are directed to their class, although all of the processing elements receive each instruction. In another embodiment, the data parallel system includes an array of processing elements and an instruction sequencer where the instruction sequencer is able to send multiple instructions. Again, the processing elements are separated in classes and execute instructions based on their class.Type: GrantFiled: December 18, 2012Date of Patent: February 7, 2017Inventors: Bogdan Mitu, Lazar Bivolarksi, Gheorghe Stefan
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Patent number: 7908461Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: GrantFiled: December 19, 2007Date of Patent: March 15, 2011Assignee: Allsearch Semi, LLCInventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20080307196Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: ApplicationFiled: May 28, 2008Publication date: December 11, 2008Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Patent number: 7451293Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: GrantFiled: October 19, 2006Date of Patent: November 11, 2008Assignee: Brightscale Inc.Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Publication number: 20080177979Abstract: A multi-core processor system includes a context area, which contains an array of stack core processing elements, a storage area that contains expensive shared resources (e.g., object cache, stack cache, and interpretation resources), and an execution area, which contains complex execution units such as an FPU and a multiply unit. The execution resources of the execution area, and the storage resources of the storage area, are shared among all the stack cores through one or more interconnection networks. Each stack core contains only frequently used resources, such as fetch, decode, context management, an internal execution unit for integer operations (except multiply and divide), and a branch unit. By separating the complex and infrequently used units (e.g., FPU or multiply/divide unit) from the simple and frequently used units in a stack core, all the complex execution resources are shared among all the stack cores, improving efficiency and processor performance.Type: ApplicationFiled: March 28, 2008Publication date: July 24, 2008Inventors: GHEORGHE STEFAN, MARIUS-CIPRIAN STOIAN
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Patent number: 7383421Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: GrantFiled: December 4, 2003Date of Patent: June 3, 2008Assignee: Brightscale, Inc.Inventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20080126757Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: ApplicationFiled: December 19, 2007Publication date: May 29, 2008Inventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20080059762Abstract: The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a bus and is able to send an instruction to the array of processing elements. The processing elements are separated into classes and only execute instructions that are directed to their class, although all of the processing elements receive each instruction. In another embodiment, the data parallel system includes an array of processing elements and an instruction sequencer where the instruction sequencer is able to send multiple instructions. Again, the processing elements are separated in classes and execute instructions based on their class.Type: ApplicationFiled: August 30, 2007Publication date: March 6, 2008Inventors: Bogdan Mitu, Gheorghe Stefan, Lazar Bivolarski
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Publication number: 20080059764Abstract: The present invention is an integral parallel machine for performing intensive computations. By combining data parallelism, time parallelism and speculative parallelism where data parallelism and time parallelism are segregated, efficient computations can be performed. Specifically, for sequential functions, the time parallel system in conjunction with an implementation for speculative parallelism is able to handle the sequential computations in a parallel manner. Each processing element in the time parallel system is able to perform a function and receives data from a prior processing element in the pipeline. Thus, after a latency period for filling the pipeline, a result is produced after clock cycle or other desired time period.Type: ApplicationFiled: August 31, 2007Publication date: March 6, 2008Inventor: Gheorghe Stefan
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Publication number: 20070226454Abstract: An MIMD processor for Java and Net processing includes a plurality of “half-processors,” separate execution units, and memory caches. Each half-processor is an MIMD processing element having resources for instruction fetch and decode and for instruction stream context management, but excluding execution resources. In other words, the execution resources are removed from the processing elements (resulting in the half-processors) and provided as separate elements for being shared by all the half-processors. The execution units, memory caches, and half-processors are operably connected by two interconnection networks that use a priority-based communications scheme for administering shared access to the execution units and memory caches by the half-processors. The MIMD machine uses a Java and/or .Net instruction set and is capable of running both separate and combined Java and .Net instructions.Type: ApplicationFiled: March 1, 2006Publication date: September 27, 2007Inventors: Marius Stoian, Gheorghe Stefan
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Publication number: 20070130444Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.Type: ApplicationFiled: October 19, 2006Publication date: June 7, 2007Inventors: Bogdan Mitu, Gheorghe Stefan, Dan Tomescu
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Patent number: 7107478Abstract: A data-processing system includes a data device for selectively storing data and an engine having access to the memory device, the engine supporting a plurality of machine executable programs. A controller is utilized which selectively outputs one of a plurality of instructions to the engine for driving the execution of the programs enabled by the engine, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the data device, the engine and the controller. The controller outputs one of the instructions to the engine for execution of one of the programs, while also executing an operation within itself, all within a single clock cycle.Type: GrantFiled: December 4, 2003Date of Patent: September 12, 2006Assignee: Connex Technology, Inc.Inventors: Dan Tomescu, Gheorghe Stefan
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Patent number: 7069386Abstract: An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.Type: GrantFiled: May 10, 2004Date of Patent: June 27, 2006Assignee: Connex Technology, Inc.Inventors: Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu
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Publication number: 20040210727Abstract: An associative memory support for a data processing system includes an associative memory device containing n-cells. A controller is provided for issuing an instruction to the associative memory device. A clock device outputs a synchronizing clock signal that includes a predetermined number of clock cycles per second, the clock device outputting the synchronizing clock signal to the associative memory device and the controller. The controller globally communicates the instruction to all of the n-cells simultaneously, within one of the clock cycles and the instruction is applied equally to each of the n-cells.Type: ApplicationFiled: May 10, 2004Publication date: October 21, 2004Applicant: GEMICER, INC.Inventors: Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu
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Patent number: 6760821Abstract: A memory engine combines associative memory and random-access memory for enabling fast string search, insertion, and deletion operations to be performed on data and includes a memory device for temporarily storing the data as a string of data characters. A controller is utilized for selectively outputting one of a plurality of commands to the memory device and receives data feedback therefrom, the memory device inspects data characters in the string in accordance with the commands outputted by the controller. A clock device is also utilized for outputting a clock signal comprised of a predetermined number of clock cycles per second to the memory device and the controller, the memory device inspecting and selectively manipulating one of the data characters within one of the clock cycles.Type: GrantFiled: August 10, 2001Date of Patent: July 6, 2004Assignee: Gemicer, Inc.Inventors: Gheorghe Stefan, Dominique Thiebaut
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Publication number: 20040123073Abstract: A data-processing system includes a data device for selectively storing data and an engine having access to the memory device, the engine supporting a plurality of machine executable programs. A controller is utilized which selectively outputs one of a plurality of instructions to the engine for driving the execution of the programs enabled by the engine, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the data device, the engine and the controller. The controller outputs one of the instructions to the engine for execution of one of the programs, while also executing an operation within itself, all within a single clock cycle.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: GEMICER, INC.Inventors: Dan Tomescu, Gheorghe Stefan
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Publication number: 20040123071Abstract: A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the associative memory device and the controller which globally communicates one of the plurality of instructions to all of the n-cells simultaneously, within one of the clock cycles.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: GEMICER, INC.Inventors: Gheorghe Stefan, Dan Tomescu
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Publication number: 20030037209Abstract: A memory engine combines associative memory and random-access memory for enabling fast string search, insertion, and deletion operations to be performed on data and includes a memory device for temporarily storing the data as a string of data characters. A controller is utilized for selectively outputting one of a plurality of commands to the memory device and receives data feedback therefrom, the memory device inspects data characters in the string in accordance with the commands outputted by the controller. A clock device is also utilized for outputting a clock signal comprised of a predetermined number of clock cycles per second to the memory device and the controller, the memory device inspecting and selectively manipulating one of the data characters within one of the clock cycles.Type: ApplicationFiled: August 10, 2001Publication date: February 20, 2003Inventors: Gheorghe Stefan, Dominique Thiebaut