Abstract: An image motion compensating address generator is disclosed including a mode selector for selecting a field mode or frame mode according to a video mode signal and a slice position signal, an address selection controller for controlling the generation of addresses according to the video mode signal and a motion coding type signal, a Y-direction read address generator for producing a Y-direction read address in units of processed block, an X-direction read address generator for dividing the processed block into four phases in the X direction and generating an X-direction read address, an X-direction write address generator for delaying the processed-block position signal and a field processed-block clock signal, and generating the X-direction write address of four phases, a Y-direction write address generator for producing a Y-direction write address, and a read & write controller for selectively outputting the X-direction and Y-direction read and write addresses according to a read/write selection toggle sign

Abstract: A memory access delay control circuit for image motion compensation in HDTV, which can adaptively delay read/write time of two frame memories and simply control the delay amount data. The circuit includes a section for providing delay amount data of a write address signal of the frame memories, a delay control section for providing delay control signal for delaying the write address signal as much as the value of the delay amount data, and an address counter section for counting and providing the write address signal in accordance with the delay control signal. According to the present invention, the delay amount data providing section may comprise a section for detecting actual delay amount of the write address signal by utilizing a frame synchronizing signal and a frame synchronizing write signal so as to automatically compensate for the inputted delay amount, thereby providing convenience in use.