Abstract: A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.

Abstract: A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.

Abstract: A data storage device includes a processor and a non-volatile memory. The processor compares a data processing size of a first command received from the host at a first time point with a reference size and divides the first command into a plurality of sub-commands when the data processing size is greater than the reference size. The data storage device further includes a memory that includes a first queue and a second queue.

Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.

Abstract: A semiconductor package substrate is provided. The package substrate includes a mold base and an interposer block embedded in the mold base, said interposer block having a plurality of vertical conductive lines therein. A metallization layer is formed on the surface of the interposer block or the mold base, said metallization layer being electrically connected to at least one of the vertical conductive lines. A semiconductor chip may be mounted on or embedded in the mold base.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.

Abstract: There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic.

Abstract: There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the top surface of the substrate so as to cover at least partially the conductive post and the semiconductor chip; and an external connection bump electrically connected to the conductive post. The system-in-package is fabricated by stacking a plurality of semiconductor chips on a top surface of a base wafer, forming a buried layer, realizing an electrical path by a conductive post, and polishing top and bottom surfaces of the package, thereby thinning the thickness of the package. Further, the system-in-package greatly improves electrical operation characteristics and increases productivity.

Abstract: There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.