Patents by Inventor Gi-Moon HONG

Gi-Moon HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240242773
    Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.
    Type: Application
    Filed: May 19, 2023
    Publication date: July 18, 2024
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Patent number: 12020775
    Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: June 25, 2024
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Dae Han Kwon
  • Publication number: 20240192925
    Abstract: A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.
    Type: Application
    Filed: May 30, 2023
    Publication date: June 13, 2024
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Patent number: 11915783
    Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Dong Yoon Ka
  • Publication number: 20240014790
    Abstract: An integrated circuit includes an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation. The integrated circuit also includes a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.
    Type: Application
    Filed: October 12, 2022
    Publication date: January 11, 2024
    Applicant: SK hynix Inc.
    Inventor: Gi Moon HONG
  • Publication number: 20230420038
    Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.
    Type: Application
    Filed: December 6, 2022
    Publication date: December 28, 2023
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Publication number: 20230282256
    Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.
    Type: Application
    Filed: July 6, 2022
    Publication date: September 7, 2023
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Publication number: 20230215476
    Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.
    Type: Application
    Filed: March 15, 2022
    Publication date: July 6, 2023
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dong Yoon KA
  • Patent number: 11688442
    Abstract: A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 27, 2023
    Assignee: SK hynix Inc.
    Inventor: Gi Moon Hong
  • Patent number: 11550355
    Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Gi Moon Hong
  • Patent number: 11489529
    Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Dae Han Kwon, Kyu Young Kim
  • Publication number: 20220345115
    Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Publication number: 20220345114
    Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON
  • Publication number: 20220328081
    Abstract: A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.
    Type: Application
    Filed: August 27, 2021
    Publication date: October 13, 2022
    Applicant: SK hynix Inc.
    Inventor: Gi Moon HONG
  • Publication number: 20220308617
    Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.
    Type: Application
    Filed: August 27, 2021
    Publication date: September 29, 2022
    Inventor: Gi Moon HONG
  • Patent number: 11418170
    Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Dae Han Kwon
  • Patent number: 11409324
    Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Kyu Dong Hwang
  • Publication number: 20220077862
    Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.
    Type: Application
    Filed: January 27, 2021
    Publication date: March 10, 2022
    Applicant: SK hynix Inc.
    Inventors: Gi Moon HONG, Dae Han KWON, Kyu Young KIM
  • Patent number: 11271549
    Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 8, 2022
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Shin Hyun Jeong, Suhwan Kim, Gi Moon Hong, Ji Hyo Kang, Jae Hyeok Yang, Dae Han Kwon, Dong Hyun Kim
  • Patent number: 11210250
    Abstract: A semiconductor apparatus may include a command receiving circuit, a multiplexing circuit, and a DQ circuit. The command receiving circuit may be configured to latch signal bits of a command according to a clock signal, and output the latched signal bits as latched signals. The multiplexing circuit may be configured to receive the latched signals from the command receiving circuit, and selectively output the latched signals according to a flag signal which is internally generated within the semiconductor apparatus. The DQ circuit may be configured to receive the selectively outputted latched signals from the multiplexing circuit and receive the flag signal, and configured to output the selectively outputted latched signals and the flag signal as a feedback command to the outside of the semiconductor apparatus through a plurality of DQ pins.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Gi Moon Hong