Patents by Inventor Gianluca Boselli

Gianluca Boselli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446537
    Abstract: In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gianluca Boselli, Muhammad Yusuf Ali
  • Patent number: 10396199
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20180366460
    Abstract: In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.
    Type: Application
    Filed: December 7, 2017
    Publication date: December 20, 2018
    Inventors: Gianluca BOSELLI, Muhammad Yusuf ALI
  • Publication number: 20170288058
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Patent number: 9711643
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Patent number: 9633991
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Patent number: 9629294
    Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: April 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Eric Kunz, Jr., Jonathan Scott Brodsky, Gianluca Boselli
  • Patent number: 9418197
    Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman, Gianluca Boselli
  • Publication number: 20160224716
    Abstract: A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman, Gianluca Boselli
  • Publication number: 20160086936
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 24, 2016
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Patent number: 9224724
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Ann Margaret Concannon, Gianluca Boselli
  • Publication number: 20150146330
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Patent number: 9035352
    Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gianluca Boselli, Rajkumar Sankaralingam
  • Publication number: 20140184237
    Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.
    Type: Application
    Filed: December 10, 2013
    Publication date: July 3, 2014
    Inventors: John Eric KUNZ, JR., Jonathan Scott BRODSKY, Gianluca BOSELLI
  • Publication number: 20130320396
    Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 5, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Akram A. SALMAN, Farzan FARBIZ, Ann Margaret CONCANNON, Gianluca BOSELLI
  • Patent number: 8589839
    Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, Jr.
  • Publication number: 20130285196
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface. A plurality of stacked ESD protection cells are in the semiconductor surface each having a surrounding isolation structure, wherein the ESD protection cells are connected in series by an interconnect and include a first ESD protection cell in series with at least a second ESD protection cell. A plurality of protection pins include a first protection pin across the first ESD protection cell but not across the second ESD protection cell to provide a first voltage rating and a second protection pin across both the first and second ESD protection cell to provide a second voltage rating which is higher than the first voltage rating.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: MARIANO DISSEGNA, GIANLUCA BOSELLI
  • Publication number: 20130285114
    Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: GIANLUCA BOSELLI, RAJKUMAR SANKARALINGAM
  • Publication number: 20130264640
    Abstract: A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AKRAM A. SALMAN, FARZAN FARBIZ, ARAVIND C. APPASWAMY, JOHN ERIC KUNZ, JR., GIANLUCA BOSELLI
  • Patent number: 8530301
    Abstract: An integrated circuit (25) formed at a semiconducting surface of a substrate including a common p-layer (38) includes functional circuitry (24) formed on the p-layer (38) including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (24). At least one ESD protection cell (30; in more detail 200) is connected to at least one of the plurality of terminals of the functional circuitry (24). The protection cell includes at least a first Nwell (37) formed in the p-layer (38), a p-doped diffusion (36) within the first Nwell (37) to form at least one Nwell diode comprising an anode (37) and a cathode (36). An NMOS transistor 200 is formed in or on the p-layer (38) comprising a n+ source (43), n+ drain (44) and a channel region comprising a p-region (41) between the source and drain, and a gate electrode (45) on a gate dielectric (46) on the channel region.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Charvaka Duvvury