Patents by Inventor Gianmauro Pozzovivo

Gianmauro Pozzovivo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903120
    Abstract: A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Patent number: 10256149
    Abstract: A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20190043757
    Abstract: A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20180247869
    Abstract: A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Patent number: 9825139
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Patent number: 9735141
    Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Michael Hutzler, Gilberto Curatola, Gianmauro Pozzovivo
  • Patent number: 9666705
    Abstract: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen, Gianmauro Pozzovivo
  • Publication number: 20170148883
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 25, 2017
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Patent number: 9564524
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Publication number: 20160247794
    Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 25, 2016
    Inventors: Martin Vielemeyer, Michael Hutzler, Gilberto Curatola, Gianmauro Pozzovivo
  • Patent number: 9373688
    Abstract: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Häberlen, Gianmauro Pozzovivo
  • Patent number: 9276097
    Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 1, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Michael Hutzler, Gilberto Curatola, Gianmauro Pozzovivo
  • Publication number: 20150349105
    Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 3, 2015
    Inventors: Gilberto Curatola, Oliver Haeberlen, Simone Lavanga, Gianmauro Pozzovivo, Fabian Reiher
  • Patent number: 8952421
    Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Patent number: 8907340
    Abstract: A semiconductor arrangement includes a semiconductor body and a semiconductor device, the semiconductor device including first and second load terminals arranged distant to each other in a first direction of the semiconductor body and a load path arranged in the semiconductor body between the first and second load terminals. The semiconductor arrangement further includes at least one Hall sensor arranged in the semiconductor body distant to the semiconductor device in a second direction perpendicular to the first direction. The Hall sensor includes two current supply terminals and two measurement terminals.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Lutz Goergens, Helmut Angerer, Gianmauro Pozzovivo, Markus Zundel
  • Patent number: 8900985
    Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Publication number: 20140103398
    Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Publication number: 20140106516
    Abstract: A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Publication number: 20130299842
    Abstract: A semiconductor device includes a semiconductor body including a plurality of compound semiconductor layers and a two-dimensional charge carrier gas channel region formed in one of the compound semiconductor layers. The semiconductor device further includes a contact structure disposed in the semiconductor body. The contact structure includes a metal region and a doped region. The metal region extends into the semiconductor body from a first side of the semiconductor body to at least the compound semiconductor layer which includes the channel region. The doped region is formed in the semiconductor body between the metal region and the channel region so that the channel region is electrically connected to the metal region through the doped region.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen, Gianmauro Pozzovivo
  • Publication number: 20130299841
    Abstract: An optocoupler includes a GaN-based photosensor disposed on a substrate and a GaN-based light source disposed on the same substrate as the GaN-based photosensor. A transparent material is interposed between the GaN-based photosensor and the GaN-based light source. The transparent material provides galvanic isolation and forms an optical channel between the GaN-based photosensor and the GaN-based light source.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 14, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Jan Ranglack, Gianmauro Pozzovivo