Patents by Inventor Gianpietro Carnevale
Gianpietro Carnevale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081074Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Changhan Kim, Gianpietro Carnevale
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Publication number: 20240069749Abstract: A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.Type: ApplicationFiled: August 21, 2023Publication date: February 29, 2024Inventors: Augusto Benvenuti, Giovanni Maria Paolucci, Alessio Urbani, Gianpietro Carnevale, Aurelio Giancarlo Mauri
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Patent number: 11832447Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 17, 2022Date of Patent: November 28, 2023Inventors: Changhan Kim, Gianpietro Carnevale
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Publication number: 20230371264Abstract: Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Albert Fayrushin, Kamal Karda, Gianpietro Carnevale, Aurelio Giancarlo Mauri
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Publication number: 20230320090Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include memory strings with a conductor channel shell and a low dielectric constant central region. In one example, memory devices, systems and methods include memory strings with a conductor channel shell and a hollow central region.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventor: Gianpietro Carnevale
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Publication number: 20230078036Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.Type: ApplicationFiled: November 16, 2022Publication date: March 16, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20230034157Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Micron Technology, Inc.Inventors: Byeung Chul Kim, Davide Resnati, Gianpietro Carnevale, Shyam Surthi
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Patent number: 11514987Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: GrantFiled: April 13, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20220278113Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Applicant: Micron Technology, Inc.Inventors: Changhan Kim, Gianpietro Carnevale
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Patent number: 11362103Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: August 6, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Changhan Kim, Gianpietro Carnevale
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Publication number: 20210233591Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Patent number: 11011236Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: GrantFiled: August 29, 2019Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20210065810Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.Type: ApplicationFiled: August 29, 2019Publication date: March 4, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Giovanni Maria Paolucci, Paolo Tessariol, Emilio Camerlenghi, Gianpietro Carnevale, Augusto Benvenuti
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Publication number: 20200365605Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Applicant: Micron Technology, Inc.Inventors: Changhan Kim, Gianpietro Carnevale
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Patent number: 10770472Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: October 31, 2018Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Changhan Kim, Gianpietro Carnevale
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Publication number: 20200135745Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Applicant: Micron Technology, Inc.Inventors: Changhan Kim, Gianpietro Carnevale
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Patent number: 9385045Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.Type: GrantFiled: August 26, 2015Date of Patent: July 5, 2016Assignee: Micron Technology, Inc.Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
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Publication number: 20150364379Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
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Patent number: 9142460Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.Type: GrantFiled: January 21, 2015Date of Patent: September 22, 2015Assignee: Micron Technology, Inc.Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
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Publication number: 20150140742Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.Type: ApplicationFiled: January 21, 2015Publication date: May 21, 2015Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale