Abstract: A multi-stage drive circuit is to be coupled to a semiconductor switch having a drive terminal, a first terminal and a second terminal, to switch the semiconductor switch on and off. The multi-stage drive circuit includes a first drive circuit, a second drive circuit and a selector circuit. The first drive circuit is to be coupled to provide a first drive signal to the drive terminal of the semiconductor switch and the second drive circuit is to be coupled to provide a second drive signal to the drive terminal of the semiconductor switch. The selector circuit is to be coupled to turn on the first and second drive circuits to provide the first and second drive signals to the drive terminal, respectively. The selector circuit turns on the second drive circuit responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value.

Abstract: An example two-way integrator includes a first current source, a second current source, a first offset current source, a second offset current source, a capacitor, a switching reference and a comparator. The capacitor integrates a sum of a first input current and a first offset current by charging with both the first current source and the first offset current source. The capacitor subsequently integrates a sum of the second input current and the second offset current by discharging with both the second current source and the second offset current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to pulses of a pulse signal. The comparator is coupled to compare the switching reference with a voltage on the capacitor.

Abstract: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.

Abstract: A multi-stage drive circuit is to be coupled to a semiconductor switch having a drive terminal, a first terminal and a second terminal, to switch the semiconductor switch on and off. The multi-stage drive circuit includes a first drive circuit, a second drive circuit and a selector circuit. The first drive circuit is to be coupled to provide a first drive signal to the drive terminal of the semiconductor switch and the second drive circuit is to be coupled to provide a second drive signal to the drive terminal of the semiconductor switch. The selector circuit is to be coupled to turn on the first and second drive circuits to provide the first and second drive signals to the drive terminal, respectively. The selector circuit turns on the second drive circuit responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value.

Abstract: A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increase in the noise generated due to rapid dv/dt during the first time period when the semiconductor switch is switching. The configuration of the circuitry to achieve this reduction in switching losses is such that benefits are less sensitive to manufacturing tolerances and temperature effects than alternative semiconductor switch drive schemes to achieve similar results.

Abstract: A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device.

Abstract: In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.

Abstract: An example two-way integrator includes a first current source, a second current source, a first offset current source, a second offset current source, a capacitor, a switching reference and a comparator. The capacitor integrates a sum of a first input current and a first offset current by charging with both the first current source and the first offset current source. The capacitor subsequently integrates a sum of the second input current and the second offset current by discharging with both the second current source and the second offset current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to pulses of a pulse signal. The comparator is coupled to compare the switching reference with a voltage on the capacitor.

Abstract: A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.

Abstract: A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: An example integrated circuit controller for a power converter includes a digital peak detector and a switching block. The digital peak detector is coupled to output a digital count signal representative of a peak input voltage of the power converter. The switching block is coupled to control switching of a power switch of the power converter to regulate an output of the power converter. The switching block is further coupled to control the switching of the power switch in response to the digital count signal.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: A simple low cost integrated circuit oscillator includes a capacitor coupled to be charged and discharged by first and second current sources. A first voltage follower circuit including a first bipolar transistor having a base is coupled to the capacitor. The first bipolar transistor is biased such that a voltage at an emitter of the first bipolar transistor follows a voltage on the capacitor. A first current path of a current mirror is coupled to the base of the first bipolar transistor. The first current path provides substantially all of a base current received by the base of the first bipolar transistor. A second voltage follower circuit including a second bipolar transistor having a base coupled to a second current path of the current mirror. The second current path provides substantially all of a base current received by the base of the second bipolar transistor.

Abstract: An apparatus providing a simple low cost integrated circuit oscillator with improved frequency stability over a range of selected frequencies by reducing the impact of process and temperature variations on a base current of bipolar transistor of the integrated circuit oscillator. A circuit includes a capacitor coupled to be alternatingly charged and discharged by first and second current sources. A first voltage follower circuit including a first bipolar transistor having a base is coupled to the capacitor. The first bipolar transistor is biased such that a voltage at an emitter of the first bipolar transistor follows a voltage on the capacitor. A current mirror having first and second current paths is included. The first current path is coupled to the base of the first bipolar transistor. The first current path provides substantially all of a base current received by the base of the first bipolar transistor.

Abstract: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal.

Abstract: A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increase in the noise generated due to rapid dv/dt during the first time period when the semiconductor switch is switching. The configuration of the circuitry to achieve this reduction in switching losses is such that benefits are less sensitive to manufacturing tolerances and temperature effects than alternative semiconductor switch drive schemes to achieve similar results.

Abstract: A frequency-to-current converter includes several capacitances with capacitive values that are effectively multiplied. After each of a series of periodic pulses, the voltage on a "ramp" capacitance is charged to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a discharge rate that is a function of a voltage on a discharge-current bias capacitance. At the end of the period, the voltage on the ramp capacitance is sampled and compared to a reference. If the voltage on the ramp capacitance is too low or too high, indicating a discharge current that is too high or too low, respectively, the bias voltage on the bias capacitance is adjusted to compensate for the error. In another embodiment, a small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels.