Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.

Abstract: A behind the ear earpiece 205 capable of multiband filtering with multiple core processors incorporated on a miniature solid state chip. The apparatus includes a plurality of microphones 305a-n and a plurality of pre-amplifiers 310a-n, an analog to digital converter 320, a digital signal processor 325 and a digital to analog converter 335 all hidden behind the ear of a user 215 with a battery. All are connected to a speaker 325 attached for producing an acoustic signal to the user 215. The method of the invention provides a compact multiband filter using a plurality of processors 405 connected to one another with single drop busses 410. Groups 415, 420, 425, 430, 435, 440, 445 and 450 520, 530, 535, 545 of processors are assigned to each particular band and each group performs multiple multiply-accumulate (“MAC”) calculations 520, 530, 535 and 545. Each MAC 520, 530, 535 and 545 is accomplished with use of the multiple registers in each core 405.

Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.

Abstract: A method and apparatus for operation of a hearing aid 205 with signal processing functions performed with an array processor 220. In one embodiment, a reconfiguration module 250 allows reconfiguration of the processors 220 in the field. Another embodiment provides wireless communication by use of earpieces 105, 110 provided with antennas 235 in communication with a user module 260. The method includes steps of converting analog data into digital data 915 filtering out noise 920 and processing the digital data in parallel 925 compensating for the user's hearing deficiencies and convert the digital data back into analog. Another embodiment adds the additional step of reconfiguring the processor in the field 1145. Yet another embodiment adds wireless communication 1040-1065.

Abstract: A processor to calculate a product-component having fewer digits than an entire product of a multiplication of a multiplicand and a multiplier. A memory holds at least one multiplicand-component having fewer digits than the multiplicand and at least one multiplier-component having fewer digits than the multiplier. A logic then calculates the product-component based on the multiplicand-components and the multiplier-components in the memory. Collectively, a plurality of the processors can calculate all of the product-components of the product.

Abstract: The invention is a method and apparatus for debugging of software on an array-type single chip computer system 16 without provision of dedicated debugging hardware on the chip. This is accomplished by suitable operating instructions that cause a hardware portion of array 16 to operate as a virtual background debug mode port 10 for one 12 and more hardware portions in the array. Virtual debug port 10 communicates with an adjacent target hardware portion 12 via their common directly connected single-drop bus 16, and with an external user interface system through an input/output (I/O) port 28, by passing the debugging information through other hardware portions 52 of the array to a peripheral hardware portion 22 adapted with the I/O port 28.