Abstract: A recovery method for a high-dimensional index structure is disclosed, in which a reinsert operation is employed based on ARIES (algorithm for recovery and isolation exploiting semantics) and a page-oriented redo and a logical undo. Further, a recording medium on which a program for carrying out the above method is recorded is disclosed, the program being readable by a computer. The recovery method for a high-dimensional index structure employing a reinsert operation according to the present invention includes the following steps. At a first step, an entry is inserted into a node, a minimum bounding region is adjusted, an overflow is processed, and a log record is stored. At a second step, the log record thus stored is recovered.

Abstract: A recovery method for a high-dimensional index structure is disclosed, in which a reinsert operation is employed based on ARIES (algorithm for recovery and isolation exploiting semantics) and a page-oriented redo and a logical undo. Further, a recording medium on which a program for carrying out the above method is recorded is disclosed, the program being readable by a computer. The recovery method for a high-dimensional index structure employing a reinsert operation according to the present invention includes the following steps. At a first step, an entry is inserted into a node, a minimum bounding region is adjusted, an overflow is processed, and a log record is stored. At a second step, the log record thus stored is recovered.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.