Patents by Inventor Gilbert Dewey
Gilbert Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230275124Abstract: Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Applicant: Intel CorporationInventors: Leonard P. Guler, Gilbert Dewey, Saurabh Morarka, Sikandar Abbas, Mohammad Hasan
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Patent number: 11742346Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.Type: GrantFiled: June 29, 2018Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher Jezewski, Ehren Mannebach, Rishabh Mehandru, Patrick Morrow, Anand S. Murthy, Anh Phan, Willy Rachmady
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Patent number: 11721735Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.Type: GrantFiled: January 20, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Gilbert Dewey, Aaron Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani, Willy Rachmady, Rishabh Mehandru, Nazila Haratipour, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Shriram Shivaraman
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Publication number: 20230238436Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.Type: ApplicationFiled: April 4, 2023Publication date: July 27, 2023Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY
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Patent number: 11699704Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.Type: GrantFiled: September 28, 2017Date of Patent: July 11, 2023Assignee: INTEL CORPORATIONInventors: Van H. Le, Marko Radosavljevic, Han Wui Then, Willy Rachmady, Ravi Pillarisetty, Abhishek Sharma, Gilbert Dewey, Sansaptak Dasgupta
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Patent number: 11695081Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.Type: GrantFiled: June 29, 2018Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Sean Ma, Nicholas Minutillo, Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel, Gilbert Dewey, Matthew Metz, Willy Rachmady
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Publication number: 20230197569Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Gilbert Dewey, Cheng-Ying Huang, Nicole K. Thomas, Marko Radosavljevic, Patrick Morrow, Ashish Agrawal, Willy Rachmady, Seung Hoon Sung, Christopher M. Neumann
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Publication number: 20230197804Abstract: Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is adjacent to the gate structure. A conductive trench contact structure is on the epitaxial source or drain structure. The conductive trench contact structure includes a first planar layer on the epitaxial source or drain structure, a second planar layer on the first planar layer, and a conductive fill material on the second planar layer.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Inventors: Nazila HARATIPOUR, Gilbert DEWEY, I-Cheng TUNG, Nancy ZELICK, Chi-Hing CHOI, Jitendra Kumar JHA, Jack T. KAVALIEROS
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Publication number: 20230193473Abstract: The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Debaleena Nandi, Gilbert Dewey, Tahir Ghani, Nazila Haratipour, Mauro J. Kobrinsky, Anand Murthy
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Publication number: 20230197800Abstract: Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact may be formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Gilbert Dewey, Cheng-Ying Huang, Nicole K. Thomas, Marko Radosavljevic, Patrick Morrow, Ashish Agrawal, Willy Rachmady, Nazila Haratipour, Seung Hoon Sung
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Publication number: 20230197817Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material on the second pEPI region.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Debaleena NANDI, Cory BOMBERGER, Diane LANCASTER, Gilbert DEWEY, Sandeep K. PATIL, Mauro J. KOBRINSKY, Anand S. MURTHY, Tahir GHANI
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Publication number: 20230197815Abstract: Techniques to form wrap-around contacts in a stacked transistor architecture. An example includes a first source or drain region and a second source or drain region spaced from and over the first source or drain region. A conductive contact is on a top surface of the second source or drain and extends down one or more side surfaces of the second source or drain region such that the conductive contact is laterally adjacent to a bottom surface of the second source or drain region. In some cases, the conductive contact is also on a top surface of the first source or drain region, and/or extends down a side surface of the first source or drain region. In some cases, a second conductive contact is on a bottom surface of the first source or drain region, and may extend up a side surface the first source or drain region.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Nicole K. Thomas, Marko Radosavljevic, Jack T. Kavalieros
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Publication number: 20230197777Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Gilbert Dewey, Cheng-Ying Huang, Nicole K. Thomas, Marko Radosavljevic, Patrick Morrow, Ashish Agrawal, Willy Rachmady, Nazila Haratipour, Seung Hoon Sung, I-Cheng Tung, Christopher M. Neumann, Koustav Ganguly, Subrina Rafique
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Publication number: 20230187509Abstract: Techniques are provided herein to form semiconductor devices having an epi region contact with a high contact area to either or both top and bottom epi regions in a stacked transistor configuration. In one example, two different semiconductor devices include an n-channel device located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A contact structure may be formed that has a greater width when contacting a top surface of the bottom source or drain region than when contacting a side surface of the top source or drain region. The higher contact area on the bottom source or drain region provides a lower contact resistance compared to previous architectures.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Urusa Alaan, Scott B. Clendenning, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Nitesh Kumar
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Publication number: 20230187356Abstract: Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Inventors: Sukru YEMENICIOUGLU, Leonard P. GULER, Gilbert DEWEY, Tahir GHANI
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Patent number: 11670682Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.Type: GrantFiled: June 2, 2021Date of Patent: June 6, 2023Assignee: Tahoe Research, Ltd.Inventors: Gilbert Dewey, Matthew V. Metz, Willy Rachmady, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Sean T. Ma, Jack T. Kavalieros
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Publication number: 20230170350Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.Type: ApplicationFiled: January 11, 2023Publication date: June 1, 2023Inventors: Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Aaron LILAK, Patrick MORROW, Anh PHAN, Ehren MANNEBACH, Jack T. KAVALIEROS
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Patent number: 11664373Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.Type: GrantFiled: December 17, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Aaron Lilak, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru
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Patent number: 11658208Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.Type: GrantFiled: March 20, 2018Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Abhishek A. Sharma, Willy Rachmady, Van H. Le, Gilbert Dewey, Ravi Pillarisetty
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Patent number: 11658222Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.Type: GrantFiled: September 27, 2017Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey, Shriram Shivaraman, Sean T. Ma, Benjamin Chu-Kung