Patents by Inventor Gilbert Meyer
Gilbert Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200133865Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL, Paul Gilbert MEYER
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Patent number: 10591977Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.Type: GrantFiled: December 10, 2015Date of Patent: March 17, 2020Assignee: Arm LimitedInventors: Mark David Werkheiser, Dominic William Brown, Ashley John Crawford, Paul Gilbert Meyer
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Publication number: 20190347217Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: ApplicationFiled: July 25, 2019Publication date: November 14, 2019Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
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Patent number: 10423466Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.Type: GrantFiled: October 18, 2016Date of Patent: September 24, 2019Assignee: Arm LimitedInventors: Ashok Kumar Tummala, Jamshed Jalal, Paul Gilbert Meyer, Dimitrios Kaseridis
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Patent number: 10402349Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: GrantFiled: February 8, 2017Date of Patent: September 3, 2019Assignee: ARM LimitedInventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
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Patent number: 10324858Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.Type: GrantFiled: June 12, 2017Date of Patent: June 18, 2019Assignee: ARM LimitedInventors: Bruce James Mathewson, Phanindra Kumar Mannava, Matthew Lucien Evans, Paul Gilbert Meyer, Andrew Brookfield Swaine
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Publication number: 20180357178Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.Type: ApplicationFiled: June 12, 2017Publication date: December 13, 2018Inventors: Bruce James MATHEWSON, Phanindra Kumar MANNAVA, Matthew Lucien EVANS, Paul Gilbert MEYER, Andrew Brookfield SWAINE
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Patent number: 10095631Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.Type: GrantFiled: December 10, 2015Date of Patent: October 9, 2018Assignee: Arm LimitedInventors: Paul Gilbert Meyer, Gurunath Ramagiri
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Publication number: 20180225214Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL, Klas Magnus BRUCE, Michael FILIPPO, Paul Gilbert MEYER, Alex James WAUGH, Geoffray Matthieu LACOURBA
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Publication number: 20180225216Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Alex James WAUGH, Geoffray LACOURBA, Paul Gilbert MEYER, Bruce James MATHEWSON, Phanindra Kumar MANNAVA
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Publication number: 20180225232Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
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Patent number: 9891976Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.Type: GrantFiled: February 26, 2015Date of Patent: February 13, 2018Assignee: ARM LimitedInventors: Andy Wangkun Chen, Mudit Bhargava, Paul Gilbert Meyer, Vikas Chandra
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Patent number: 9809005Abstract: Anti-ballistic systems and methods for making same are described. The anti-ballistic systems may be formed from various materials arranged in a structure, such as a wall structure. For example, an anti-ballistic system may be formed from a metal material, a polymer material, and a stone material. In some embodiments, the metal material may include aluminum (for example, an aluminum composite panel), the polymer material may include ethylene vinyl acetate, and the stone material may include granite. The anti-ballistic wall systems may be configured to be resistant to ballistics, blasts, and/or forced entry.Type: GrantFiled: October 5, 2015Date of Patent: November 7, 2017Assignee: Antiballistic Security and Protection, Inc.Inventors: Richard Grieves, Gilbert Meyer, Leif Lundkvist
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Publication number: 20170168548Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.Type: ApplicationFiled: December 10, 2015Publication date: June 15, 2017Applicant: ARM LimitedInventors: Mark David WERKHEISER, Dominic William BROWN, Ashley John CRAWFORD, Paul Gilbert MEYER
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Publication number: 20170168876Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.Type: ApplicationFiled: October 18, 2016Publication date: June 15, 2017Applicant: ARM LimitedInventors: Ashok Kumar TUMMALA, Jamshed JALAL, Paul Gilbert MEYER, Dimitrios KASERIDIS
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Publication number: 20170168954Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.Type: ApplicationFiled: December 10, 2015Publication date: June 15, 2017Applicant: ARM LimitedInventors: Paul Gilbert MEYER, Gurunath RAMAGIRI
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Publication number: 20160102471Abstract: Anti-ballistic systems and methods for making same are described. The anti-ballistic systems may be formed from various materials arranged in a structure, such as a wall structure. For example, an anti-ballistic system may be formed from a metal material, a polymer material, and a stone material. In some embodiments, the metal material may include aluminum (for example, an aluminum composite panel), the polymer material may include ethylene vinyl acetate, and the stone material may include granite. The anti-ballistic wall systems may be configured to be resistant to ballistics, blasts, and/or forced entry.Type: ApplicationFiled: October 5, 2015Publication date: April 14, 2016Inventors: Richard GRIEVES, Gilbert MEYER, Leif LUNDKVIST
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Patent number: 8977837Abstract: At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The at least one instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is to be executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry.Type: GrantFiled: May 27, 2009Date of Patent: March 10, 2015Assignee: ARM LimitedInventors: Robert Gregory McDonald, Paul Gilbert Meyer
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Patent number: 8255629Abstract: A storage apparatus receives a first and second access requests for accessing items in a same clock cycle. The apparatus includes two stores, each storing a subset of the plurality of items, the first access request being routed to a first store and the second access request to a second store; miss detecting circuitry for detecting a miss in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in one of the two stores, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first or second store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.Type: GrantFiled: June 22, 2009Date of Patent: August 28, 2012Assignee: ARM LimitedInventors: Paul Gilbert Meyer, David James Williamson, Simon John Craske
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Publication number: 20100325358Abstract: A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Applicant: ARM LimitedInventors: Paul Gilbert Meyer, David James Williamson, Simon John Craske