Patents by Inventor Gilbert W. Dewey

Gilbert W. Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193814
    Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Gilbert W. Dewey, Rafael Rios, Van H. Le, Jack T. Kavalieros
  • Patent number: 11004982
    Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
  • Patent number: 10992017
    Abstract: Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Gilbert W. Dewey, Hyung-Jin Lee
  • Patent number: 10964820
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Jack T. Kavalieros
  • Patent number: 10964992
    Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Henning Braunisch, Gilbert W. Dewey, Telesphor Kamgaing, Hyung-Jin Lee, Johanna M. Swan
  • Publication number: 20210074825
    Abstract: Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Patent number: 10892335
    Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Gilbert W. Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200411428
    Abstract: Disclosed herein are memory devices with a logic region between memory regions. For example, in some embodiments, a memory device may include: a first memory region; a second memory region; a logic region between the first memory region and the second memory region; and a metallization stack, wherein the first memory region is between the logic region and the metallization stack.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Gilbert W. Dewey, Willy Rachmady, Prashant Majhi, Hui Jae Yoo, Cheng-Ying Huang, Ehren Mannebach
  • Patent number: 10818799
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Patent number: 10811461
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey
  • Publication number: 20200295127
    Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Aaron D. Lilak, Anh Phan, Cheng-Ying Huang, Gilbert W. Dewey, Patrick Morrow, Rishabh Mehandru, Roza Kotlyar, Sean T. Ma, Willy Rachmady
  • Publication number: 20200295003
    Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: Gilbert W. Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Kimin Jun, Patrick Morrow, Aaron D. Lilak, Ehren Mannebach, Anh Phan
  • Publication number: 20200294939
    Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.
    Type: Application
    Filed: April 25, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Georgios Dogiamis, Telesphor Kamgaing, Gilbert W. Dewey, Hyung-Jin Lee
  • Publication number: 20200280121
    Abstract: Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Telesphor Kamgaing, Gilbert W. Dewey, Hyung-Jin Lee
  • Publication number: 20200266218
    Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Gilbert W. Dewey, Willy Rachmady, Rishabh Mehandru, Ehren Mannebach, Cheng-Ying Huang, Anh Phan, Patrick Morrow, Kimin Jun
  • Publication number: 20200185457
    Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.
    Type: Application
    Filed: August 29, 2017
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Publication number: 20200185501
    Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Gilbert W. Dewey, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Cheng-Ying Huang, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200098926
    Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Brian S. Doyle, Elijah V. Karpov, Prashant Majhi, Gilbert W. Dewey, Benjamin Chu-Kung, Van H. Le, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200083225
    Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Aaron D. Lilak, Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Gilbert W. Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200058705
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey