Patents by Inventor Gilles Montoriol

Gilles Montoriol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10431534
    Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
  • Patent number: 10418972
    Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: September 17, 2019
    Assignee: NXP B.V.
    Inventors: Stephane Thuries, Cristian Pavao Moreira, Gilles Montoriol
  • Publication number: 20190181079
    Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.
    Type: Application
    Filed: January 8, 2018
    Publication date: June 13, 2019
    Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
  • Patent number: 10230378
    Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 12, 2019
    Assignee: NXP B.V.
    Inventors: Stephane Thuries, Cristian Pavao Moreira, Gilles Montoriol
  • Publication number: 20190013797
    Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analogue signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analogue signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.
    Type: Application
    Filed: May 8, 2018
    Publication date: January 10, 2019
    Inventors: Stephane Thuries, Cristian Pavao Moreira, Gilles Montoriol
  • Publication number: 20190013814
    Abstract: The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analogue signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analogue signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 10, 2019
    Inventors: Stephane Thuries, Cristian Pavao Moreira, Gilles Montoriol
  • Patent number: 9973360
    Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP USA, Inc.
    Inventors: Olivier Vincent Doare, Dominique Delbecq, Gilles Montoriol
  • Patent number: 9835715
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Dominique Delbecq, Olivier Doare, Gilles Montoriol
  • Patent number: 9711471
    Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: July 18, 2017
    Assignee: NXP USA, Inc.
    Inventors: Charaf-Eddine Souria, Gilles Montoriol, St├ęphane Damien Thuries
  • Publication number: 20170180169
    Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 22, 2017
    Inventors: Olivier Vincent Doare, Dominique Delbecq, Gilles Montoriol
  • Publication number: 20170141057
    Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.
    Type: Application
    Filed: April 18, 2016
    Publication date: May 18, 2017
    Inventors: Charaf-Eddine Souria, Gilles Montoriol, St├ęphane Damien Thuries
  • Patent number: 9628093
    Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: April 18, 2017
    Assignee: NXP USA, INC.
    Inventors: Birama Goumballa, Gilles Montoriol, Didier Salle
  • Patent number: 9401723
    Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gilles Montoriol, Olivier Vincent Doare, Birama Goumballa, Didier Salle
  • Publication number: 20160182064
    Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 23, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Birama GOUMBALLA, Gilles Montoriol, Didier SALLE
  • Publication number: 20160173109
    Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.
    Type: Application
    Filed: May 12, 2015
    Publication date: June 16, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: GILLES MONTORIOL, OLIVIER VINCENT DOARE, BIRAMA GOUMBALLA, DIDIER SALLE
  • Publication number: 20160109559
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Application
    Filed: March 17, 2015
    Publication date: April 21, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DOMINIQUE DELBECQ, OLIVIER DOARE, GILLES MONTORIOL
  • Patent number: 9094032
    Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephane Dugalleix, Birama Goumballa, Gilles Montoriol
  • Publication number: 20140252570
    Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 11, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: GILLES MONTORIOL, THIERRY DELAUNAY, FREDERIC TILHAC
  • Publication number: 20140152481
    Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
    Type: Application
    Filed: July 20, 2011
    Publication date: June 5, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Stephane Dugalleix, Birama Goumballa, Gilles Montoriol
  • Patent number: 8736034
    Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gilles Montoriol, Jr., Thierry Delaunay, Frederic Tilhac