Abstract: An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Abstract: A wireless communication unit (100) comprises a transmitter (120) arranged to transmit an envelope modulated signal. The transmitter (120) comprises a radio frequency power amplifier (124) operably coupled to a logarithmic detector (210, 310) and a bias control circuit (126) arranged to set a direct current bias level of the radio frequency power amplifier (124) via a bias signal. The logarithmic detector (210, 310) is arranged to detect the envelope modulated signal and provide the detected envelope modulated signal to the bias control circuit such that the bias signal applied to the radio frequency power amplifier (124) comprises both a direct current and a low frequency component based on the detected envelope modulated signal. In this manner, the present invention supports a tradeoff of linearity for additional efficiency, as well as providing more margin on adjacent channel power levels, whilst maintaining a good overall power added efficiency.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: A radio frequency device comprises a radio frequency (RF) power amplifier (PA) operably coupled to a protection circuit for minimising voltage standing wave ratio effects, wherein the protection circuit comprises a current limiter indexed to a power supplied to the RF PA. In this manner, the protection circuit combines detection of both current and voltage increase in order to provide a direct feedback on the final RF PA stage via a bias control.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: A radio frequency (RF) power amplification circuit including a power amplifier is provided for preventing breakdown of the power amplifier. The power amplifier includes an input for receiving RF signals and an output for providing amplified RF signals. The RF power amplification circuit also includes a bias circuit coupled to the input of the power amplifier to permit normal operation of the power amplifier when the base current is below a predetermined current threshold and to prevent normal operation of the power amplifier when the base current is above the predetermined current threshold.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.

Abstract: A radio frequency (RF) power amplification circuit including a power amplifier is provided for preventing breakdown of the power amplifier. The power amplifier includes an input for receiving RF signals and an output for providing amplified RF signals. The RF power amplification circuit also includes a bias circuit coupled to the input of the power amplifier to permit normal operation of the power amplifier when the base current is below a predetermined current threshold and to prevent normal operation of the power amplifier when the base current is above the predetermined current threshold.

Abstract: An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance.