Abstract: The invention relates to a control method for a multi-core processor comprising a plurality of cores sharing at least one common material resource according to a sharing policy based on different time windows, each time window being attributed to least one core. The control method comprises the anticipation of a request to be emitted by a software application run by a core and requiring a transaction between said core and the common resource, the planning of the transaction in a time window to be attributed said core for access to the common resource, the implementation of the planned transaction and the loading of the data into a private cache memory of said core, and the restitution of the data to the software application from the private cache memory.

Abstract: A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.

Abstract: A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.

Abstract: A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.

Abstract: A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.

Abstract: The invention concerns a data compaction method and system for an intermediate program. The method consists in searching the program (1000) for identical sequences (Si) and counting Ni number of occurrences of each sequence (Si), a comparison test (1001) to find the superiority of a function f(Ni) to a reference value enables to generate (1003) a specific instruction of a specific code (Ci) with which the sequence (Si) is associated, replacing (1004) each occurrence in the sequence (Si) by the specific code (Ci) in the intermediate program to create a compacted intermediate program (FCC) with which an executing file (FEX) is associated. The invention is applicable to multiple application portable objects such as microprocessor cards, onboard systems of the like.