Patents by Inventor Gireesh Rajendran

Gireesh Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10281575
    Abstract: In an embodiment of the present disclosure, a Radar transceiver for object detection comprises a two dimensional antenna array receiving plurality of a reflected radio frequency (RF) signals, a mux-adder selectively adding the reflected RF signals in first mode and selectively multiplexing the reflected RF signals in a second mode, a range bin detector determining a valid range bins in the first mode and a three dimensional (3D) image reconstructor operating on the valid range bins to reconstruct a 3D image of the object in the second mode. In that the two dimensional antenna array comprises antenna elements arranged in K rows and M columns, and the mux-adder adds a RF signal received on the M columns of each row in the first mode. The mux-adder multiplexes the RF signal received on the M columns of each row in the second mode.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 7, 2019
    Assignee: Steradian Semiconductors Private Limited
    Inventors: Gireesh Rajendran, Apu Sivadas
  • Patent number: 10284271
    Abstract: A beam steering device comprising a set of phase shifters, each providing substantially same phase shift, connected such that output of one phase shifter feeds the input of other, in that a signal is cascaded through the set of phase shifters to generate a corresponding set of phase shifted signals, and an array of antennas forming the RF radiation beam. The set of phase shifted signals are coupled to the respective one of antenna in the array of antennas so as to steer the RF radiation beam in accordance with the phase shift. The device further comprises a set of mixer to translate the first set of phase shifted signals to a RF canter frequency.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 7, 2019
    Assignee: Steradian Semiconductors Private Limited
    Inventors: Gireesh Rajendran, Rakesh Kumar
  • Publication number: 20180088229
    Abstract: In an embodiment of the present disclosure, a Radar transceiver for object detection comprises a two dimensional antenna array receiving plurality of a reflected radio frequency (RF) signals, a mux-adder selectively adding the reflected RF signals in first mode and selectively multiplexing the reflected RF signals in a second mode, a range bin detector determining a valid range bins in the first mode and a three dimensional (3D) image reconstructor operating on the valid range bins to reconstruct a 3D image of the object in the second mode. In that the two dimensional antenna array comprises antenna elements arranged in K rows and M columns, and the mux-adder adds a RF signal received on the M columns of each row in the first mode. The mux-adder multiplexes the RF signal received on the M columns of each row in the second mode.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 29, 2018
    Inventors: Gireesh Rajendran, Apu Sivadas
  • Patent number: 9893702
    Abstract: A notch filter including an inductor-capacitor tuning circuit is disclosed. The inductor-capacitor tuning circuit may determine a frequency response of the notch filter in accordance with an associated resonant frequency. In some exemplary embodiments, the inductor-capacitor circuit may include a differential inductor divided at a symmetry point and a variable capacitor coupled to the differential inductor at the symmetry point.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Apu Sivadas
  • Patent number: 9722536
    Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gireesh Rajendran, Rakesh Kumar, Subhashish Mukherjee, Ashish Lachhwani
  • Patent number: 9692375
    Abstract: Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9660585
    Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ayush Mittal, Gireesh Rajendran, Rahul Karmaker
  • Patent number: 9608569
    Abstract: A method and apparatus for linearizing a baseband filter are provided. The apparatus is configured to, via a first conducting module, receive a first current signal. The apparatus is further configured to, via a converting module, receive a second current signal, generate a voltage signal based on the second current signal, and apply the voltage signal to the first conducting module. An amount of the second current signal received by the converting module is based on an amount of the first current signal flowing through the first conducting module. The apparatus is also configured to, via a second conducting module, control an output current signal based on the voltage signal. The output current signal is controlled to be a linear replica of the first current signal for in-band frequencies.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: March 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Bhushan Shanti Asuri, Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9595919
    Abstract: Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 14, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Ashish Lachhwani
  • Patent number: 9594388
    Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path. A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhishek Agrawal, Yogesh Darwhekar, Gireesh Rajendran
  • Publication number: 20170033750
    Abstract: Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.
    Type: Application
    Filed: September 17, 2015
    Publication date: February 2, 2017
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20170033757
    Abstract: A notch filter including an inductor-capacitor tuning circuit is disclosed. The inductor-capacitor tuning circuit may determine a frequency response of the notch filter in accordance with an associated resonant frequency. In some exemplary embodiments, the inductor-capacitor circuit may include a differential inductor divided at a symmetry point and a variable capacitor coupled to the differential inductor at the symmetry point.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 2, 2017
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Apu Sivadas
  • Patent number: 9554413
    Abstract: One aspect of an apparatus for wireless communications is disclosed. The apparatus includes a controller, a first transceiver, and a second transceiver. The first transceiver is configurable by the controller to support first communications through a cellular network to at least one of a packet-based network and a circuit-switched network. The second transceiver configurable by the controller to operate with the first transceiver to support first communications through the cellular network in a first mode and support second communications through an access point to the packet-based network in a second mode. In an aspect, the second transceiver is further configured to switch from the first mode to the second mode by moving its wireless connection from the cellular network to the access point while maintaining a network-layer connection to the cellular network.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: January 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Gangadhar Burra, MeeLan Lee, Gireesh Rajendran, Anup Savla, Jeremy Lin, Soumya Das, Bongyong Song
  • Publication number: 20160380592
    Abstract: Apparatus includes: a mixer configured to mix local a oscillator signal with a baseband signal and output a radio frequency (RF) signal; a first load coupled to the mixer and tuned to an operating frequency; and a second load coupled to the mixer and tuned to a predetermined multiple of the operating frequency.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Gireesh Rajendran, Alok Prakash Joshi, Ashish Lachhwani
  • Publication number: 20160373062
    Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Ayush Mittal, Gireesh Rajendran, Rahul Karmaker
  • Publication number: 20160294327
    Abstract: A method and apparatus for linearizing a baseband filter are provided. The apparatus is configured to, via a first conducting module, receive a first current signal. The apparatus is further configured to, via a converting module, receive a second current signal, generate a voltage signal based on the second current signal, and apply the voltage signal to the first conducting module. An amount of the second current signal received by the converting module is based on an amount of the first current signal flowing through the first conducting module. The apparatus is also configured to, via a second conducting module, control an output current signal based on the voltage signal. The output current signal is controlled to be a linear replica of the first current signal for in-band frequencies.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 6, 2016
    Inventors: Bhushan Shanti ASURI, Alok Prakash JOSHI, Gireesh RAJENDRAN
  • Publication number: 20160234876
    Abstract: One aspect of an apparatus for wireless communications is disclosed. The apparatus includes a controller, a first transceiver, and a second transceiver. The first transceiver is configurable by the controller to support first communications through a cellular network to at least one of a packet-based network and a circuit-switched network. The second transceiver configurable by the controller to operate with the first transceiver to support first communications through the cellular network in a first mode and support second communications through an access point to the packet-based network in a second mode. In an aspect, the second transceiver is further configured to switch from the first mode to the second mode by moving its wireless connection from the cellular network to the access point while maintaining a network-layer connection to the cellular network.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventors: Gangadhar BURRA, MeeLan LEE, Gireesh RAJENDRAN, Anup SAVLA, Jeremy LIN, Soumya DAS, Bongyong SONG
  • Publication number: 20160226488
    Abstract: Disclosed is circuitry for operating a switch which sees high voltage swings across its source, gate, drain, and bulk terminals. The circuitry generates one or more bias voltages in proportion to an input voltage swing. The one or more bias voltages may be used to bias the gate and bulk terminals to provide reliable and improved turn OFF performance in the switch.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9385901
    Abstract: A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gireesh Rajendran, Gurkanwal Singh Sahota, Rakesh Kumar
  • Publication number: 20160142231
    Abstract: A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 19, 2016
    Inventors: Gireesh Rajendran, Gurkanwal Singh Sahota, Rakesh Kumar