Patents by Inventor Gireesh Rajendran

Gireesh Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949763
    Abstract: According to an aspect, a method of data compression in a radar system comprising, converting a plurality of ranges in a first data form into a polar form, determining a plurality of logarithmic values of the plurality of ranges in the polar form, quantising the plurality of logarithmic values of the plurality of ranges with a first bit width that is fewer than a second bit width in the first data form. According to another aspect, the method further comprising quantizing the logarithmic magnitude part with a third bit width and quantising the logarithmic phase part with a fourth bit width.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 2, 2024
    Inventors: Amrith Sukumaran, G Ranjithkumar, Gireesh Rajendran
  • Publication number: 20240006736
    Abstract: According to an aspect, method of combining a plurality of powers in an integrated circuit comprising receiving the plurality of powers on corresponding a plurality of primary coils, wherein each primary coil in the plurality of primary coils comprising a coupling part and a non-coupling part, coupling the plurality of powers to a secondary coil through only the coupling part, wherein the coupling part of every primary coil in the plurality of primary coils is inductively coupled to the secondary coil and nullifying power in the non-coupling part of a primary coils in the plurality of primary coil.
    Type: Application
    Filed: December 29, 2022
    Publication date: January 4, 2024
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Gireesh Rajendran, Alok Prakash Joshi
  • Publication number: 20230296451
    Abstract: According to an aspect, a temperature sensor in a chip for determining a chip temperature comprises a first temperature sensor with a first characteristic, a second temperature sensor with a second characteristic, first characteristic being different from the second characteristic, a processor operative to determine the chip temperature is configured to determine a first parameter and a second parameter in the calibration mode and determining the chip temperature using the first parameter and the second parameter in a real time operating mode, wherein, the first parameter is derived from a first relation between the first characteristic and the second characteristic and the second parameter is at least based on first parameter.
    Type: Application
    Filed: July 1, 2022
    Publication date: September 21, 2023
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Gireesh Rajendran, G. Ranjithkumar
  • Patent number: 11693107
    Abstract: According to an aspect, a radar system comprising a transmitter operative to transmit a first set of chirps on a single transmit antenna and a second set of chirps on a plurality of transmit antennas, in that, the first set of chirps forming a first part of a chirp frame and the second set of chirps forming a second part of the chirp frame, a first receiver segment operative to generate a first set of parameters from a first set of received chirps that is reflection of the first set of chirps from one or more objects and a second segment operative to generate a second set of parameters from a second set of received chirps that is reflection of the second set of chirps from the one or more objects part of the received chirp frame and the first set of parameters, wherein, first set of parameters and second set of parameters comprise at least one of range doppler and angle of one or more objects.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: July 4, 2023
    Inventors: Gireesh Rajendran, Ankit Sharma, Sai Gunaranjan Pelluri, Apu Sivadas
  • Publication number: 20230204715
    Abstract: According to an aspect, a method of determining Doppler in a radar system comprising receiving a set of chirps, sampling in time the set of chirps to generate a set of non-uniform samples with one sample per chirp that is non-uniform in time in each chirp across the set of chirps, generating a first Doppler frequency from the set of non-uniform samples, generating a set of non-aliased Doppler frequencies for the first Doppler frequencies from a corresponding set of hypothesis, determining a first set of angles of arrival for every non-aliased Doppler frequency in the a set of non-aliased Doppler frequencies and selecting a first non-aliased Doppler frequency in the set of non-aliased Doppler frequencies that corresponds to the first angle of arrival with a minimum error in the a set of angles of arrival.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 29, 2023
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Apu Sivadas, Gireesh Rajendran, Sai Gunaranjan Pelluri, Ankit Sharma
  • Publication number: 20230152436
    Abstract: According to an aspect, a method of determining two dimensional (2D) angle of arrival (AoA) in a radar system comprising determining one dimensional (1D) AoA to generate a first set of (AoA), selecting a set of valid 1D AoA angles from the first set AoA, and determining the 2D AoA from the set of valid 1D AoA, Wherein the 1D AoA is determined on a first set of data received over a first uniform linear antenna array arranged in the first axis and the 2D AoA is determined on a second set data received over the first and the second MIMO antenna array arranged in the second axis and the set of valid 1D AoA in the first axis. Wherein the second antenna array need not be orthogonal to the first linear antenna array.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 18, 2023
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Ankit Sharma, Dibakar Sil, Sai Gunaranjan Pelluri, Apu Sivadas, Gireesh Rajendran
  • Patent number: 11625056
    Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.
    Type: Grant
    Filed: July 31, 2021
    Date of Patent: April 11, 2023
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 11601088
    Abstract: According to an aspect, a tank circuit in an integrated circuit comprising a plurality of metal strips forming a first part of a closed contour enclosing a first area, a set of split sections forming a second part and geometrically aligned with the closed contour, and a plurality of capacitors coupled between the split sections to form the tank circuit, wherein a first flux linkage due a current flowing in the set of split sections pass through the first area in the same direction as that of a second flux linkage due to the current flowing in the plurality of metal strips, and the set of split sections and the plurality of metal strips together forming an inductance coil.
    Type: Grant
    Filed: September 5, 2020
    Date of Patent: March 7, 2023
    Inventor: Gireesh Rajendran
  • Publication number: 20220291705
    Abstract: According to an aspect a low noise electronic voltage regulator comprises a regulating transistor operative to regulate an input DC voltage to provide a regulated DC output voltage, an error amplifier configured to generate an error signal based on a reference voltage and a feedback voltage, wherein the error amplifier receiving the feedback voltage through a feedback loop formed between the regulated DC output voltage and the feedback voltage, and a first amplifier in the feedback loop providing a gain of greater than unity from the regulated DC output voltage and the feedback voltage.
    Type: Application
    Filed: July 31, 2021
    Publication date: September 15, 2022
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Publication number: 20220099819
    Abstract: According to an aspect, a radar system comprising a transmitter operative to transmit a first set of chirps on a single transmit antenna and a second set of chirps on a plurality of transmit antennas, in that, the first set of chirps forming a first part of a chirp frame and the second set of chirps forming a second part of the chirp frame, a first receiver segment operative to generate a first set of parameters from a first set of received chirps that is reflection of the first set of chirps from one or more objects and a second segment operative to generate a second set of parameters from a second set of received chirps that is reflection of the second set of chirps from the one or more objects part of the received chirp frame and the first set of parameters, wherein, first set of parameters and second set of parameters comprise at least one of range doppler and angle of one or more objects.
    Type: Application
    Filed: December 15, 2020
    Publication date: March 31, 2022
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Gireesh Rajendran, Ankit Sharma, Sai Gunaranjan Pelluri, Apu Sivadas
  • Publication number: 20210399684
    Abstract: According to an aspect, a tank circuit in an integrated circuit comprising a plurality of metal strips forming a first part of a closed contour enclosing a first area, a set of split sections forming a second part and geometrically aligned with the closed contour, and a plurality of capacitors coupled between the split sections to form the tank circuit, wherein a first flux linkage due a current flowing in the set of split sections pass through the first area in the same direction as that of a second flux linkage due to the current flowing in the plurality of metal strips, and the set of split sections and the plurality of metal strips together forming an inductance coil.
    Type: Application
    Filed: September 5, 2020
    Publication date: December 23, 2021
    Applicant: Steradian Semiconductors Private Limited
    Inventor: Gireesh Rajendran
  • Patent number: 11115032
    Abstract: According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: September 7, 2021
    Inventors: Ashish Lachhwani, Gireesh Rajendran
  • Patent number: 11092686
    Abstract: A method in a time switched multiple input and multiple output (MIMO) radar system comprising, receiving (610) from an antenna array a plurality of data points representing a radar signal reflected from plurality of objects, forming (620) a first set of beams from the plurality of data points, wherein the first set of beams are making a first set angles with a normal to the antenna array, detecting a set of objects (410A-L) from the first set of beams, determining (630) a set of Doppler frequencies of the set of objects, computing (650) a self-velocity representing a velocity of the antenna array from the set of Doppler frequencies and the first set of angles, and correcting (660) the plurality of data points using the self-velocity and a second set of angles to generate plurality of corrected data points.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 17, 2021
    Inventors: Gireesh Rajendran, Apu Sivadas
  • Patent number: 11047972
    Abstract: A multichannel radar system comprising a set of antennas each receiving a sequence of chirps reflected from plurality of objects, a range detector generating a set of range bins for each chirp, a beam former operative to generate a set of dominant frequency components from a group of range bins picked from the set of range bins across the set of antennas, a nearness detector for separating the set of dominant frequencies into a first set of dominant frequencies and a second set of dominant frequencies, a frequency subtractor configured to shift the each dominant frequency in the first set of dominant frequencies by its phase by a first value to form a third set of phase shifted dominant frequencies, and a Doppler estimator estimating a Doppler frequency of the each dominant frequency in the set of dominant frequencies from the third set of phase shifted dominant frequencies and the second set of dominant frequencies.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 29, 2021
    Inventors: Apu Sivadas, Gireesh Rajendran
  • Patent number: 11041941
    Abstract: An object detection system comprises a first object detection unit detecting an object from a first radio frequency (RF) signal data comprising first set of characteristics representing a first object, a second object detection unit detecting the object from an optical image data and a calibration unit calibrating the first RF signal data from the optical image data, in that, the second object detection unit and the first object detection unit are aligned to detect the object in a first region.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: June 22, 2021
    Inventors: Gireesh Rajendran, Apu Sivadas
  • Patent number: 10784215
    Abstract: According to an aspect of the present invention, an electronic system (499) operative on a millimeter signal comprises an integrated circuit (401) comprising a first solder ball (420A) and a second solder ball (420B) respectively coupled to a positive and a negative signal interface points (412 and 413) of a differential millimeter signal on a die (410) housed in the integrated circuit (401), wherein the first and the second solder balls (420A and 420B) are positioned one behind other from an edge of the integrated circuit (401) and a three-path coplanar waveguide (CPW) comprising a center path (495B) and a two adjacent paths (495A and 495C) formed on a printed circuit board (PCB) (490) such that the center path (495B) is coupled to the first solder ball that is in front and the two adjacent paths coupled to the second solder ball that is behind the first solder ball.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 22, 2020
    Inventors: Apu Sivadas, Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 10784878
    Abstract: According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: September 22, 2020
    Inventors: Amrith Sukumaran, Gireesh Rajendran, Ashish Lachhwani
  • Patent number: 10734966
    Abstract: According to an aspect of present disclosure, a phase shifter for providing a desired phase shift to a very high frequency signal fabricated as part of the an integrated circuit comprises a first coil segment and a second coil segment together forming an inductor of first inductance value, a first capacitor of first capacitance value electrically connected parallel the inductor, a second capacitor of second capacitance value electrically connected between the first coil segment and the second coil segment and a resistor of a first resistance value electrically connected parallel to the second capacitor, in that, the inductor, first capacitor, second capacitor and the resistor together operative as a phase shifter such that when a input signal of a first frequency is presented across the first capacitor, the output signal across the resistor is phase shifted version of the input signal shifted in phase by a first angle.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 4, 2020
    Inventors: Alok Prakash Joshi, Gireesh Rajendran, Rakesh Kumar
  • Publication number: 20200241125
    Abstract: A multichannel radar system comprising a set of antennas each receiving a sequence of chirps reflected from plurality of objects, a range detector generating a set of range bins for each chirp, a beam former operative to generate a set of dominant frequency components from a group of range bins picked from the set of range bins across the set of antennas, a nearness detector for separating the set of dominant frequencies into a first set of dominant frequencies and a second set of dominant frequencies, a frequency subtractor configured to shift the each dominant frequency in the first set of dominant frequencies by its phase by a first value to form a third set of phase shifted dominant frequencies, and a Doppler estimator estimating a Doppler frequency of the each dominant frequency in the set of dominant frequencies from the third set of phase shifted dominant frequencies and the second set of dominant frequencies.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 30, 2020
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Apu Sivadas, Gireesh Rajendran
  • Publication number: 20200161257
    Abstract: According to an aspect of the present invention, an electronic system (499) operative on a millimeter signal comprises an integrated circuit (401) comprising a first solder ball (420A) and a second solder ball (420B) respectively coupled to a positive and a negative signal interface points (412 and 413) of a differential millimeter signal on a die (410) housed in the integrated circuit (401), wherein the first and the second solder balls (420A and 420B) are positioned one behind other from an edge of the integrated circuit (401) and a three-path coplanar waveguide (CPW) comprising a center path (495B) and a two adjacent paths (495A and 495C) formed on a printed circuit board (PCB) (490) such that the center path (495B) is coupled to the first solder ball that is in front and the two adjacent paths coupled to the second solder ball that is behind the first solder ball.
    Type: Application
    Filed: February 4, 2019
    Publication date: May 21, 2020
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Apu Sivadas, Alok Prakash Joshi, Gireesh Rajendran