Patents by Inventor Giri N. K. Rangan
Giri N. K. Rangan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9893718Abstract: A transmission driver impedance calibration circuit and method. A circuit is disclosed that includes: a controller for controlling a set of switches; a comparator having an output that is coupled to the controller; and a first comparator input coupled to: a first selectable node coupled between a first p-type adjustable resistor segment (PSEG) and an external resistor; and a second selectable node coupled between a pair of internal resistors; and a second comparator input coupled to: a third selectable node coupled between a second PSEG and a tcoil resistor, the tcoil resistor being further coupled in series to a n-type adjustable resistor segment (NSEG); and a fourth selectable node coupled between the tcoil resistor and the NSEG.Type: GrantFiled: October 17, 2016Date of Patent: February 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Suhas Shivaram, Giri N. K. Rangan
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Patent number: 9595943Abstract: A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.Type: GrantFiled: October 8, 2014Date of Patent: March 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Santhosh Madhavan, Giri N. K. Rangan, Patrick I. Rosno, Timothy J. Schmerbeck
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Generating a parallel data signal by converting serial data of a serial data signal to parallel data
Patent number: 9542354Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.Type: GrantFiled: July 15, 2014Date of Patent: January 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Steven M. Clements, John F. Ewen, Giri N. K. Rangan, Shridha Tyagi, Arun R. Umamaheswaran -
Publication number: 20160105161Abstract: A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Inventors: Santhosh Madhavan, Giri N. K. Rangan, Patrick l. Rosno, Timothy J. Schmerbeck
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Patent number: 9252801Abstract: A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.Type: GrantFiled: March 31, 2014Date of Patent: February 2, 2016Assignee: Intersil Americas LLCInventors: Giri N K Rangan, Roger Levinson, John M. Caruso
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GENERATING A PARALLEL DATA SIGNAL BY CONVERTING SERIAL DATA OF A SERIAL DATA SIGNAL TO PARALLEL DATA
Publication number: 20160019182Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.Type: ApplicationFiled: July 15, 2014Publication date: January 21, 2016Inventors: STEVEN M. CLEMENTS, JOHN F. EWEN, GIRI N.K. RANGAN, SHRIDHA TYAGI, ARUN R. UMAMAHESWARAN -
Patent number: 8872587Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.Type: GrantFiled: March 6, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Rajesh Cheeranthodi, John F. Ewen, Santhosh Madhavan, Giri N. K. Rangan, Umesh K. Shukla, Sarabjeet Singh
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Publication number: 20140253236Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: RAJESH CHEERANTHODI, JOHN F. EWEN, SANTHOSH MADHAVAN, GIRI N.K. RANGAN, UMESH K. SHUKLA, SARABJEET SINGH
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Patent number: 8271567Abstract: A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient.Type: GrantFiled: September 12, 2008Date of Patent: September 18, 2012Assignee: Intersil Americas Inc.Inventors: Santosh Nene, Giri N. K. Rangan
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Patent number: 8093985Abstract: Circuits, methods, and apparatus that provide highly accurate DCPs. One example provides a DCP that includes a resistor string having taps that may be selected by a corresponding number of switches under the control of a digital word. To compensate for parasitic switch resistances and for variations in the values of the resistor sting caused by processing tolerances, a voltage-controlled resistor (VCR) is placed in parallel with the resistor string and switches. A control voltage generated using a control loop adjusts the parallel VCR such that the resistance seen across the DCP is the desired value. The control loop compares a reference resistor to loop components that are scaled to the resistor string, switches, and VCR. The reference resistor may be an external resistor or an internal resistor. If the resistor is internal, it may be trimmed, for example with lasers or fuses.Type: GrantFiled: October 1, 2008Date of Patent: January 10, 2012Assignee: Intersil Americas Inc.Inventors: Lokesh Kumath, Giri N. K. Rangan
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Patent number: 7786912Abstract: A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.Type: GrantFiled: December 3, 2007Date of Patent: August 31, 2010Assignee: Intersil Americas Inc.Inventors: Giri N K Rangan, Roger Levinson, John M Caruso
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Patent number: 7737795Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.Type: GrantFiled: November 29, 2007Date of Patent: June 15, 2010Inventors: Giri N. K. Rangan, Earl E. Swartzlander, Jr.
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Publication number: 20090083354Abstract: A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient.Type: ApplicationFiled: September 12, 2008Publication date: March 26, 2009Applicant: INTERSIL AMERICAS INC.Inventors: Santosh Nene, Giri N.K. Rangan
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Publication number: 20080129393Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.Type: ApplicationFiled: November 29, 2007Publication date: June 5, 2008Inventors: Giri N.K. Rangan, Earl E. Swartzlander
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Patent number: 6885900Abstract: A method and apparatus for providing multiple channel audio in a computing system includes processing that begins by receiving an audio setup signal that indicates whether audio is to be outputted as stereo audio or multiple channel audio. When multiple channel audio is to be outputted, the line-in driver is disabled in the audio processing circuitry and the multiple channel driver of the audio processing circuitry is enabled. Thus, the multiple channel driver is operably coupled to the line-in audio jack. When the audio output is to be outputted as stereo audio, the multiple channel driver is disabled and the line-in driver is enable. Thus, the line-in driver is operably coupled to the line-in audio jack.Type: GrantFiled: July 10, 2000Date of Patent: April 26, 2005Assignee: Sigmatel, Inc.Inventors: Mathew A Rybicki, Giri N. K. Rangan, Kenneth G Ifesinachukwa
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Patent number: 6861968Abstract: A digital-to-analog converter (“DAC”) system utilizes notch filters and chopping modulation technology to remove l/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency and all harmonics equal to approximately one-half of a digital input signal sampling frequency. A notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Another notch filter attenuating signals having frequencies around twice the chopping frequency further reduces fold back of noise into the baseband.Type: GrantFiled: September 23, 2003Date of Patent: March 1, 2005Assignee: Cirrus Logic, Inc.Inventors: John L. Melanson, Stephen T. Hodapp, Giri N. K. Rangan
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Patent number: 6842486Abstract: A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.Type: GrantFiled: April 29, 2003Date of Patent: January 11, 2005Assignee: Cirrus Logic, Inc.Inventors: Marjorie R. Plisch, John L. Melanson, Stephen T. Hodapp, Giri N. K. Rangan
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Publication number: 20040141558Abstract: A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.Type: ApplicationFiled: April 29, 2003Publication date: July 22, 2004Inventors: Marjorie R. Plisch, John L. Melanson, Stephen T. Hodapp, Giri N. K. Rangan
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Publication number: 20040140922Abstract: A digital-to-analog converter (“DAC”) system utilizes notch filters and chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency and all harmonics equal to approximately one-half of a digital input signal sampling frequency. A notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Another notch filter attenuating signals having frequencies around twice the chopping frequency further reduces fold back of noise into the baseband.Type: ApplicationFiled: September 23, 2003Publication date: July 22, 2004Inventors: John L. Melanson, Stephen T. Hodapp, Giri N. K. Rangan