Patents by Inventor Girish Anathahalli Singrigowda

Girish Anathahalli Singrigowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11463084
    Abstract: A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: October 4, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thanapandi Ganesan, Prateek Mishra, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Animesh Jain, Girish Anathahalli Singrigowda
  • Patent number: 11418189
    Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadeesh Anathahalli Singrigowda, Ashish Sahu, Rajesh Mangalore Anand, Aniket Bharat Waghide, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Patent number: 11418187
    Abstract: A power supply detection circuit for an integrated circuit (IC) includes a reference voltage circuit and a comparator circuit. The reference voltage circuit produces a reference voltage from the supply voltage at a reference voltage node. The comparator circuit includes a first p-type metal oxide semiconductor (PMOS) transistor with a source coupled to a positive supply terminal, a gate receiving the reference voltage, and a drain connected to a comparator output terminal. A first n-type metal oxide semiconductor (NMOS) transistor has a drain connected to the comparator output terminal, a source connected to the negative supply terminal, and a gate receiving a second voltage that varies relative to the supply voltage. A second PMOS transistor has a source coupled to the positive supply terminal, a gate connected to the reference voltage node, and a drain providing the second voltage and coupled to a filter.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: August 16, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ashish Sahu, Aniket Bharat Waghide, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Publication number: 20210409020
    Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 30, 2021
    Inventors: Jagadeesh Anathahalli Singrigowda, Ashish Sahu, Rajesh Mangalore Anand, Aniket Bharat Waghide, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Patent number: 10715139
    Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 14, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajesh Mangalore Anand, Jagadeesh Anathahalli Singrigowda, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Publication number: 20200076429
    Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Rajesh Mangalore Anand, Jagadeesh Anathahalli Singrigowda, Girish Anathahalli Singrigowda, Prasant Kumar Vallur