Patents by Inventor Giuseppe Curello
Giuseppe Curello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10332871Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.Type: GrantFiled: March 18, 2016Date of Patent: June 25, 2019Assignee: Intel IP CorporationInventors: Christian Cornelius Russ, Giuseppe Curello, Tomasz Biedrzycki, Franz Kuttner, Luis F. Giles, Bernhard Stein
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Publication number: 20170271322Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.Type: ApplicationFiled: March 18, 2016Publication date: September 21, 2017Inventors: Christian Cornelius Russ, Giuseppe Curello, Tomasz Biedrzycki, Franz Kuttner, Luis F. Giles, Bernhard Stein
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Patent number: 8741720Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: April 5, 2013Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20130224926Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: April 5, 2013Publication date: August 29, 2013Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chai-Hong Jan, Mark T. Bohr
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Patent number: 8426927Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: May 13, 2011Date of Patent: April 23, 2013Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Patent number: 8174060Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: March 4, 2011Date of Patent: May 8, 2012Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 8154067Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: April 6, 2009Date of Patent: April 10, 2012Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Publication number: 20110215422Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20110157854Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: March 4, 2011Publication date: June 30, 2011Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 7943468Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: March 31, 2008Date of Patent: May 17, 2011Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20090242998Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20090189193Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: INTEL CORPORATIONInventors: GIUSEPPE CURELLO, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 7560780Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.Type: GrantFiled: December 8, 2005Date of Patent: July 14, 2009Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
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Patent number: 7541239Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: June 30, 2006Date of Patent: June 2, 2009Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 7482670Abstract: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.Type: GrantFiled: May 24, 2006Date of Patent: January 27, 2009Assignee: Intel CorporationInventors: Giuseppe Curello, Thomas Hoffmann, Mark Armstrong
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Publication number: 20080311720Abstract: A method of forming a transistor comprising: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.Type: ApplicationFiled: July 11, 2008Publication date: December 18, 2008Inventors: Thomas Hoffman, Sunit Tyagi, Giuseppe Curello, Berhard Sell, Christopher Auth
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Patent number: 7422950Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.Type: GrantFiled: December 14, 2005Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Giuseppe Curello, Hemant V. Deshpande, Sunit Tyagi, Mark Bohr
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Patent number: 7335959Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.Type: GrantFiled: January 6, 2005Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: Giuseppe Curello, Bernhard Sell, Sunit Tyagi, Chris Auth
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Publication number: 20080003746Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Giuseppe Curello, Ian R. Post, Chai-Hong Jan, Mark Bohr
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Publication number: 20070145495Abstract: A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.Type: ApplicationFiled: December 27, 2005Publication date: June 28, 2007Inventors: Giuseppe Curello, Sivakumar Mudanai, Nick Lindert, Leonard Pipes, M. Shaheed, Sunit Tyagi