Patents by Inventor Giuseppe Ferla

Giuseppe Ferla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9191072
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 17, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Patent number: 9154188
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 6, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Publication number: 20140045309
    Abstract: A vertical conduction power device includes respective gate, source and drain areas in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations may be provided by a first metallization level. The gate, source and drain terminals may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge. A sinker structure extends perpendicularly to the substrate and may be formed by a grid of sinkers located below both the first parallel regions and the second closed region.
    Type: Application
    Filed: September 30, 2013
    Publication date: February 13, 2014
    Inventors: FERRUCCIO FRISINA, GIUSEPPE FERLA, ANGELO MAGRI'
  • Patent number: 8624332
    Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magrì
  • Patent number: 8482085
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: July 9, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Patent number: 8420487
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 16, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Publication number: 20120171953
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Publication number: 20120168520
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Application
    Filed: March 8, 2012
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Patent number: 8013384
    Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giuseppe Arena, Giuseppe Ferla, Marco Camalleri
  • Publication number: 20110089491
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 21, 2011
    Applicant: STMicroelectronics, S.r.l.
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Publication number: 20110081759
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 7, 2011
    Applicant: STMicroelectronics, S.r.l.
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Patent number: 7875936
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Publication number: 20090321826
    Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c
    Type: Application
    Filed: September 1, 2009
    Publication date: December 31, 2009
    Applicant: STMicroelectronics, S.r.l.
    Inventors: Giuseppe ARENA, Giuseppe Ferla, Marco Camalleri
  • Patent number: 7601610
    Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: October 13, 2009
    Assignee: STMicroelectronics, S.r.L.
    Inventors: Giuseppe Arena, Giuseppe Ferla, Marco Camalleri
  • Patent number: 7569883
    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 4, 2009
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri, Antonio Giuseppe Grimaldi, Gaetano Bazzano
  • Publication number: 20090033467
    Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Finocchiaro, Giovanni Girlando, Giuseppe Palmisano, Giuseppe Ferla, Alberto Pagani
  • Patent number: 7304335
    Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: December 4, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Magri', Ferruccio Frisina, Giuseppe Ferla, Marco Camalleri
  • Publication number: 20060244059
    Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.
    Type: Application
    Filed: November 21, 2005
    Publication date: November 2, 2006
    Inventors: Angelo Magri, Ferruccio Frisina, Giuseppe Ferla
  • Publication number: 20060220121
    Abstract: Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.
    Type: Application
    Filed: November 21, 2005
    Publication date: October 5, 2006
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri, Antonio Grimaldi, Gaetano Bazzano