Patents by Inventor Giuseppe Giandonato

Giuseppe Giandonato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4890281
    Abstract: The switching element for self-routing multistage packet-switching interconnection networks comprises: an input unit, composed of as many sections (IMA, IMB) as the element inputs are, each section comprising a FIFO memory (FIFA, FIFB) for packet buffering; a switch (SW) associated with a control unit (SCU) which, for each packet to be forwarded, sets up the connection requested for that packet between one input and one or more outputs of the element (ECP), on the ground of a routing tag associated with each packet and comprising a first and a second portion relative to normal routing and to broadcasting in the different stages of the network (RC), and solves possible routing conflicts between packets simultaneously arriving at different inputs; and an output unit, composed of as many sections (RU0, RU1) as the element outputs are and performing the whole of the functions necessary for the correct packet forwarding towards a destination.
    Type: Grant
    Filed: November 6, 1987
    Date of Patent: December 26, 1989
    Assignee: Cselt - Centro Studi E Laboratori Telecomunicazioni S.P.A.
    Inventors: Gian P. Balboni, Giuseppe Giandonato, Riccardo Melen, Vinicio Vercellone
  • Patent number: 4366535
    Abstract: A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal.
    Type: Grant
    Filed: January 14, 1980
    Date of Patent: December 28, 1982
    Assignee: CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
    Inventors: Riccardo Cedolin, Wolmer Chiarottino, Giuseppe Giandonato, Silvano Giorcelli, Giorgio Martinengo, Giorgio Sofi, Sergio Villone
  • Patent number: 4356547
    Abstract: An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus--if the latter is available--whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points.
    Type: Grant
    Filed: December 27, 1979
    Date of Patent: October 26, 1982
    Assignee: CSELT--Centro Studi e Laboratori Telecomunicazioni S.p.A.
    Inventors: Valerio Barcaroli, Carlo DeMichelis, Giuseppe Giandonato, Silvano Giorcelli
  • Patent number: 4335446
    Abstract: At a subscriber station AU communicating with a central office of a data network, a logic unit UM includes a processing subunit UE which, under the control of a microprogrammed subunit UC comprising a microinstruction memory MM and a sequencer SQ, digitally demodulates an incoming carrier and synthesizes an outgoing carrier modulated in the DPSK (differential-phase-shift keying) mode. The modulation is effected by multiplying stored bits of an outgoing signal, read out from a data memory MD, with bits representing digitized sine and cosine samples of the carrier wave obtained from a calculator AL within subunit UE, followed by conversion to analog form and filtering; demodulation is carried out in a similar manner, after conversion of analog samples of the incoming carrier to digital form, by multiplying the resulting bits with those of the calculated sine and cosine samples.
    Type: Grant
    Filed: December 6, 1979
    Date of Patent: June 15, 1982
    Assignee: CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
    Inventors: Francesco Gandini, Giuseppe Giandonato, Enrico Impallomeni, Roberto Montagna