Patents by Inventor Giuseppe Guarnaccia
Giuseppe Guarnaccia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409320Abstract: In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.Type: ApplicationFiled: May 30, 2023Publication date: December 21, 2023Inventors: Antonino Giuseppe Fontana, Giuseppe Guarnaccia, Stefano Catalano
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Publication number: 20230055842Abstract: A semiconductor device comprises one or more registers having digital signals stored therein. The semiconductor device is configured for communication with one or more external devices and such communication may involve requests for access to portions of these register or registers. Register shield circuitry is provided comprising access detection circuitry configured to detect requests for access to these register portions in communication with the external device or devices. The register shield circuitry is configured to be selectively activated in a register shield mode to shield these register portions from undesired requests for access. When activated in the register shield mode, the register shield circuitry prevents access to these register portions in response to requests for access detected by the access detection circuitry.Type: ApplicationFiled: August 5, 2022Publication date: February 23, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Salvatore Marco ROSSELLI, Giuseppe GUARNACCIA
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Patent number: 11456857Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.Type: GrantFiled: June 6, 2019Date of Patent: September 27, 2022Assignee: STMICROELECTRONICS S.r.l.Inventors: Rosalino Critelli, Giuseppe Guarnaccia
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Patent number: 11281807Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.Type: GrantFiled: May 3, 2019Date of Patent: March 22, 2022Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Rosalino Critelli, Giuseppe Guarnaccia, Delphine Le-Goascoz, Nicolas Anquet
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Patent number: 11042655Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.Type: GrantFiled: March 7, 2019Date of Patent: June 22, 2021Assignee: STMICROELECTRONICS S.r.l.Inventors: Giuseppe Guarnaccia, Rosalino Critelli
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Patent number: 10635394Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.Type: GrantFiled: January 24, 2019Date of Patent: April 28, 2020Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Marco Rosselli, Giuseppe Guarnaccia
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Patent number: 10540277Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.Type: GrantFiled: October 15, 2014Date of Patent: January 21, 2020Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
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Publication number: 20190386816Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.Type: ApplicationFiled: June 6, 2019Publication date: December 19, 2019Inventors: Rosalino Critelli, Giuseppe Guarnaccia
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Publication number: 20190354726Abstract: In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.Type: ApplicationFiled: May 3, 2019Publication date: November 21, 2019Inventors: Rosalino Critelli, Giuseppe Guarnaccia, Delphine Le-Goascoz, Nicolas Anquet
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Patent number: 10419432Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.Type: GrantFiled: October 17, 2014Date of Patent: September 17, 2019Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble2) SAS, STMicroelectronics S.R.L.Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
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Publication number: 20190278926Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.Type: ApplicationFiled: March 7, 2019Publication date: September 12, 2019Inventors: Giuseppe GUARNACCIA, Rosalino CRITELLI
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Publication number: 20190265947Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.Type: ApplicationFiled: January 24, 2019Publication date: August 29, 2019Inventors: Salvatore Marco Rosselli, Giuseppe Guarnaccia
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Patent number: 9727306Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.Type: GrantFiled: October 7, 2014Date of Patent: August 8, 2017Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe Guarnaccia, Salvatore Marco Rosselli
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Patent number: 9660936Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.Type: GrantFiled: October 16, 2014Date of Patent: May 23, 2017Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Riccardo Locatelli, Michael Soulie, Francesco Giotta, Raffaele Guarrasi, Giuseppe Guarnaccia
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Publication number: 20160246714Abstract: A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.Type: ApplicationFiled: October 15, 2014Publication date: August 25, 2016Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Giuseppe Maruccia, Giuseppe Guarnaccia, Raffaele Guarrasi
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Publication number: 20160226878Abstract: An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.Type: ApplicationFiled: October 17, 2014Publication date: August 4, 2016Inventors: Michael Soulie, Riccardo Locatelli, Valerio Catalano, Hajer Ferjani, Giuseppe Maruccia, Raffaele Guarrasi, Giuseppe Guarnaccia
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Patent number: 9311975Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.Type: GrantFiled: October 7, 2014Date of Patent: April 12, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Salvatore Marco Rosselli, Giuseppe Guarnaccia, Ugo Mari
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Publication number: 20160099032Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Salvatore Marco ROSSELLI, Giuseppe GUARNACCIA, Ugo MARI
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Publication number: 20160099031Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Inventors: Giuseppe GUARNACCIA, Salvatore Marco ROSSELLI
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Publication number: 20150109916Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.Type: ApplicationFiled: October 16, 2014Publication date: April 23, 2015Inventors: Riccardo Locatelli, Michael Soulie, Francesco Giotta, Raffaele Guarrasi, Giuseppe Guarnaccia