Patents by Inventor Glen Andrew Harris
Glen Andrew Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028241Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.Type: ApplicationFiled: July 22, 2022Publication date: January 25, 2024Inventors: Yasuo ISHII, Steven Daniel MACLEAN, Nicholas Andrew PLANTE, Muhammad Umar FAROOQ, Michael Brian SCHINZLER, Nicholas Todd HUMPHRIES, Glen Andrew HARRIS
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Patent number: 11663014Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, following instructions that appear after the status updating instruction in the instruction stream.Type: GrantFiled: August 26, 2019Date of Patent: May 30, 2023Assignee: ARM LIMITEDInventors: Abhishek Raja, Rakesh Shaji Lal, Michael Filippo, Glen Andrew Harris, Vasu Kudaravalli, Huzefa Moiz Sanjeliwala, Jason Setter
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Patent number: 11204773Abstract: A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.Type: GrantFiled: September 7, 2018Date of Patent: December 21, 2021Assignee: Arm LimitedInventors: William Elton Burky, Glen Andrew Harris, Yasuo Ishii
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Publication number: 20210064377Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.Type: ApplicationFiled: August 26, 2019Publication date: March 4, 2021Inventors: . ABHISHEK RAJA, Rakesh Shaji LAL, Michael FILIPPO, Glen Andrew HARRIS, Vasu KUDARAVALLI, Huzefa Moiz SANJELIWALA, Jason SETTER
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Publication number: 20200081719Abstract: A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.Type: ApplicationFiled: September 7, 2018Publication date: March 12, 2020Inventors: William Elton BURKY, Glen Andrew HARRIS, Yasuo ISHII
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Patent number: 10310862Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.Type: GrantFiled: March 21, 2017Date of Patent: June 4, 2019Assignee: ARM LimitedInventors: Robert Greg McDonald, Michael Filippo, Glen Andrew Harris
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Publication number: 20180275994Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventors: Robert Greg McDONALD, Michael FILIPPO, Glen Andrew HARRIS
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Patent number: 9946545Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.Type: GrantFiled: November 16, 2010Date of Patent: April 17, 2018Assignee: ARM LimitedInventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
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Patent number: 9081581Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.Type: GrantFiled: November 16, 2010Date of Patent: July 14, 2015Assignee: ARM LimitedInventors: James Nolan Hardage, Conrado Blasco Allue, Glen Andrew Harris
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Publication number: 20150082007Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.Type: ApplicationFiled: November 20, 2014Publication date: March 19, 2015Inventors: Glen Andrew HARRIS, James Nolan HARDAGE, Mark Carpenter GLASS
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Patent number: 8972701Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.Type: GrantFiled: December 6, 2011Date of Patent: March 3, 2015Assignee: ARM LimitedInventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
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Patent number: 8914615Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.Type: GrantFiled: December 2, 2011Date of Patent: December 16, 2014Assignee: ARM LimitedInventors: Glen Andrew Harris, James Nolan Hardage, Mark Carpenter Glass
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Publication number: 20130145126Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicant: ARM LIMITED,Inventors: Glen Andrew Harris, James Nolan Hardage, Mark Carpenter Glass
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Publication number: 20130145127Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: ARM LIMITEDInventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
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Patent number: 8386754Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.Type: GrantFiled: June 24, 2009Date of Patent: February 26, 2013Assignee: ARM LimitedInventors: Conrado Blasco Allue, David James Williamson, James Nolan Hardage, Glen Andrew Harris, Robert Gregory McDonald
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Publication number: 20120124337Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: ARM LIMITEDInventors: James Nolan Hardage, Conrado Blasco Allue, Glen Andrew Harris
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Publication number: 20120124346Abstract: A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: ARM LIMITEDInventors: James Nolan Hardage, Conrado Blasco Allue, Glen Andrew Harris, David James Williamson
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Publication number: 20120124301Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: ARM LIMITEDInventors: James Nolan Hardage, Glen Andrew Harris, Mark Carpenter Glass
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Patent number: 7958335Abstract: A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit.Type: GrantFiled: August 5, 2005Date of Patent: June 7, 2011Assignee: ARM LimitedInventors: Conrado Blasco Allue, Glen Andrew Harris, Stephen John Hill
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Publication number: 20100332805Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Applicant: ARM LimitedInventors: Conrado Blasco Allue, David James Williamson, James Nolan Hardage, Glen Andrew Harris, Robert Gregory McDonald