Patents by Inventor Glenn A. Glass

Glenn A. Glass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056592
    Abstract: An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani
  • Patent number: 11024713
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11024737
    Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 11011620
    Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass, Jiong Zhang, Ritesh Jhaveri, Szuya S. Liao
  • Patent number: 11004954
    Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 11004978
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Patent number: 10998270
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 10985263
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10978568
    Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Mark R. Brazier, Anand S. Murthy, Tahir Ghani, Owen Y. Loh
  • Publication number: 20210083116
    Abstract: Techniques are disclosed for performing silicon (Si) substrate modification to enable formation of a thin, relaxed germanium (Ge)-based layer on the modified Si substrate. The thin, relaxed, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the modification of the Si substrate, where such modification may include depositing a modification layer or performing ion implantation in/on the Si substrate. The modification layer can be characterized by the nucleation of defects which predominantly terminate within the Si substrate or the Ge-based layer, rather than running through to the top of the Ge-based layer.
    Type: Application
    Filed: June 30, 2017
    Publication date: March 18, 2021
    Applicant: INTEL CORPORATION
    Inventors: KARTHIK JAMBUNATHAN, CORY C. BOMBERGER, GLENN A. GLASS, ANAND S. MURTHY, JU H. NAM, TAHIR GHANI
  • Publication number: 20210074823
    Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.
    Type: Application
    Filed: October 28, 2020
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky
  • Patent number: 10944006
    Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Chandra S. Mohapatra, Hei Kam, Nabil G. Mistkawi, Jun Sung Kang, Biswajeet Guha
  • Patent number: 10930738
    Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Dipanjan Basu, Seung Hoon Sung, Glenn A. Glass, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20210020632
    Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 21, 2021
    Applicant: INTEL CORPORATION
    Inventors: Nabil G. Mistkawi, Glenn A. Glass
  • Publication number: 20210013199
    Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: INTEL CORPORATION
    Inventors: Nabil G. Mistkawi, Glenn A. Glass
  • Patent number: 10892337
    Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 12, 2021
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky
  • Publication number: 20210005722
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 7, 2021
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20210005748
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 7, 2021
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20210005712
    Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY
  • Patent number: 10886408
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma