Patents by Inventor Glenn J. Hinton

Glenn J. Hinton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190243558
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: Eric J. Dahlen, Glenn J. HINTON, Raj K. RAMANUJAN
  • Patent number: 10365832
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Publication number: 20190220406
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
  • Patent number: 10241912
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
  • Publication number: 20180341588
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 29, 2018
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Glenn J. HINTON
  • Patent number: 10102126
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Glenn J. Hinton
  • Patent number: 10048868
    Abstract: Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Alaa R. Alameldeen, Glenn J. Hinton, Blaise Fanning, James J. Greensky
  • Publication number: 20180181411
    Abstract: A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Michael A. Rothman, Vincent J. Zimmer, Glenn J. Hinton, Barnes Cooper, Leena K. Puthiyedath
  • Publication number: 20180095674
    Abstract: In one embodiment, an inter-memory transfer interface having selective data compression/decompression in accordance with the present description, selects from multiple candidate processes, a compression/decompression process to compress a region of data from a near memory before transmitting the compressed data to the far memory. In another aspect, the inter-memory transfer interface stores metadata indicating the particular compression/decompression process selected to compress that region of data. The stored metadata may then be used to identify the compression/decompression technique selected to compress a particular region of data, for purposes of locating the compressed data and subsequently decompressing data of that region when read from the far memory. Other aspects are described herein.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Alaa R. ALAMELDEEN, Glenn J. HINTON, Blaise FANNING, Robert J. ROYER, JR., James J. GREENSKY
  • Publication number: 20180088822
    Abstract: Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Alaa R. Alameldeen, Glenn J. Hinton, Blaise Fanning, James J. Greensky
  • Publication number: 20180004432
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Application
    Filed: June 26, 2017
    Publication date: January 4, 2018
    Inventors: Eric J. DAHLEN, Glenn J. HINTON, Raj K. RAMANUJAN
  • Publication number: 20170249250
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Application
    Filed: March 13, 2017
    Publication date: August 31, 2017
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Kai CHENG, Taarinya POLEPEDDI, Camille C. RAAD, David J. ZIMMERMAN, Muthukumar P. SWAMINATHAN, Dimitrios ZIAKAS, Mohan J. KUMAR, Bassam N. COURY, Glenn J. HINTON
  • Patent number: 9703562
    Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: William C. Rash, Bret L. Toll, Scott D. Hahn, Glenn J. Hinton
  • Patent number: 9690493
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Patent number: 9600416
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
  • Patent number: 9594648
    Abstract: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr
  • Publication number: 20170031821
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Application
    Filed: June 24, 2016
    Publication date: February 2, 2017
    Inventors: Raj K. RAMANUJAN, Rajat AGARWAL, Glenn J. HINTON
  • Patent number: 9423959
    Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: August 23, 2016
    Assignee: Intel Corporation
    Inventors: Subramanya R. Dulloor, Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Richard A. Uhlig, Robert S. Chappell, Joseph Nuzman, Kai Cheng, Sailesh Kottapalli, Yen-Cheng Liu, Mohan Kumar, Raj K. Ramanujan, Glenn J. Hinton
  • Patent number: 9418700
    Abstract: A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Glenn J. Hinton, David J. Zimmerman
  • Patent number: 9378142
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Glenn J. Hinton