Patents by Inventor Gobi Padmanabhan

Gobi Padmanabhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5874754
    Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: February 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Jasopin Lee, Gobi Padmanabhan, Abraham Yee, Stanley Yeh
  • Patent number: 5796130
    Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: August 18, 1998
    Assignee: LSI Logic Corporation
    Inventors: Tim Carmichael, Gobi Padmanabhan, Abraham Yee, Stanley Yeh
  • Patent number: 5721151
    Abstract: A plurality of macro-arrays are formed on a semiconductor substrate. Each macro-array includes a logic area in which a plurality of interconnectable logic gates are formed, and an Input/Output (I/O) area in which a plurality of I/O devices are formed. I/O terminals are formed outside the I/O area, which enable the logic devices of the macro-arrays to be interconnected with the logic devices of the other macro-arrays via the I/O devices. Alternatively, connections can be made directly to the logic devices. The interconnections are made using a pattern of conductors such that the macro-arrays are linked to form a composite gate array which provides a programmed logical functionality. A number of contiguous macro-arrays which provide the required number of gates are used, with the unused macro-arrays being cut away and discarded.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 24, 1998
    Assignee: LSI Logic Corporation
    Inventors: Gobi Padmanabhan, Abraham Yee
  • Patent number: 5717238
    Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: February 10, 1998
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi Padmanabhan, Douglas T. Grider, Chi-Yi Kao
  • Patent number: 5621616
    Abstract: A semiconductor integrated circuit includes a semiconductor circuit chip housed in a package. The package provides for electrical interface of the integrated circuit chip with external circuitry, and also provides environmental protection for the circuit chip. The circuit chip includes a circuit portion which liberates heat into the semiconductor substrate of the chip during operation of the integrated circuit. The integrated circuit chip also includes a layer of insulative material which overlies the semiconductor substrate. A thermally conductive plug member penetrates through the layer of insulative material and extends into a hole formed in the semiconductor substrate. This plug member is in conductive heat transfer relation with the material of the semiconductor substrate, and connects thermally with high-conductivity heat transfer structure conducting heat from the substrate to the package for liberation to the ambient.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: April 15, 1997
    Assignee: LSI Logic Corporation
    Inventors: Alexander H. Owens, Gobi Padmanabhan
  • Patent number: 5585286
    Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: December 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi Padmanabhan, Douglas T. Grider, Chi-Yi Kao
  • Patent number: 5440154
    Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: August 8, 1995
    Assignee: LSI Logic Corporation
    Inventors: Tim Carmichael, Gobi Padmanabhan, Abraham Yee, Stanley Yeh
  • Patent number: 5358886
    Abstract: An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: October 25, 1994
    Assignee: LSI Logic Corporation
    Inventors: Abraham Yee, Stanley Yeh, Tim Carmichael, Gobi Padmanabhan