Patents by Inventor Gordon A. Haller

Gordon A. Haller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180307412
    Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.
    Type: Application
    Filed: January 2, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Publication number: 20180294272
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Application
    Filed: October 30, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • Patent number: 10090318
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Patent number: 10083984
    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jie Li, James Mathew, Kunal Shrotri, Luan C. Tran, Gordon A. Haller, Yangda Zhang, Hongpeng Yu, Minsoo Lee
  • Patent number: 10038002
    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
  • Publication number: 20180204851
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Publication number: 20180190540
    Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 31, 2016
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Jun Liu, Gordon A. Haller, Fei Wang, Wei Yeeng Ng, Wesley O. McKinsey, Zhiqiang Xie, Jeremy F. Adams, Hongbin Zhu, Jun Zhao, Mark A. Levan
  • Patent number: 10002767
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Gordon A. Haller, Fatma A. Simsek-Ege
  • Publication number: 20180130819
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 10, 2018
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Publication number: 20180108669
    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 19, 2018
    Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
  • Publication number: 20180096955
    Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Minsoo Lee, Gordon A. Haller, Philip J. Ireland
  • Patent number: 9935120
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Grant
    Filed: February 21, 2016
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Publication number: 20180069015
    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 8, 2018
    Inventors: Hongbin Zhu, Lijing Gou, Gordon Haller, Luan C. Tran
  • Publication number: 20180040626
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Patent number: 9857989
    Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Jun Zhao, Gowrisankar Damarla, David A. Daycock, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu, Matthew R. Park, Prakash Rau Mokhna Rau
  • Publication number: 20170365617
    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.
    Type: Application
    Filed: August 17, 2017
    Publication date: December 21, 2017
    Inventors: Jie Li, James Mathew, Kunal Shrotri, Luan C. Tran, Gordon A. Haller, Yangda Zhang, Hongpeng Yu, Minsoo Lee
  • Patent number: 9847340
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • Patent number: 9842847
    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Lijing Gou, Gordon Haller, Luan C. Tran
  • Patent number: 9773805
    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jie Li, James Mathew, Kunal Shrotri, Luan C. Tran, Gordon A. Haller, Yangda Zhang, Hongpeng Yu, Minsoo Lee
  • Patent number: 9741734
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil