Patents by Inventor Gordon A. Haller

Gordon A. Haller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170229470
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Publication number: 20170170190
    Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Applicant: Intel Corporation
    Inventors: Hongbin Zhu, Jun Zhao, Purnima Narayanan, Gordon Haller, Damir Fazil
  • Patent number: 9659949
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Publication number: 20170140941
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Hongbin ZHU, Gordon A. HALLER, Fatma A. SIMSEK-EGE
  • Patent number: 9595531
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Hongbin Zhu, Gordon A Haller, Fatma A Simsek-Ege
  • Patent number: 9530683
    Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, James Matthew, Jie Sun, Gordon Haller
  • Patent number: 9520402
    Abstract: Embodiments of the present disclosure are directed towards techniques to provide etch stops to the wordlines that form a staircase structure of a 3D memory array. In one embodiment, the apparatus may comprise a 3D memory array having wordlines disposed in a staircase structure. A wordline may include a silicide layer and a spacer disposed to abut the silicide layer around an end of the wordline. The silicide layer and the spacer may form an etch stop of the wordline for a wordline contact structure to electrically connect the wordline with the memory array in response to a deposition of the wordline contact structure on the etch stop. The etch stop may be configured to prevent a physical or electrical contact of the wordline contact structure with an adjacent wordline of the staircase structure, in order to avoid undesired short circuits. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Gordon A. Haller, Jun Liu
  • Publication number: 20160284719
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Publication number: 20160233225
    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Hongbin Zhu, Lijing Gou, Gordon Haller, Luan C. Tran
  • Patent number: 9397210
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Publication number: 20160172373
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Application
    Filed: February 21, 2016
    Publication date: June 16, 2016
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Publication number: 20160133640
    Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.
    Type: Application
    Filed: July 11, 2014
    Publication date: May 12, 2016
    Inventors: HONGBIN ZHU, GORDON A. HALLER, FATMA A. SIMSEK-EGE
  • Patent number: 9305844
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 9287379
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Patent number: 9281402
    Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller
  • Publication number: 20150333143
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: Micron Technology, Inc.
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Publication number: 20150279851
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • Patent number: 9076888
    Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Thomas A. Figura, Gordon A. Haller, Ravi Iyer, John Mark Meldrim, Justin Harnish
  • Publication number: 20150162246
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Publication number: 20150064871
    Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: John Hopkins, James Matthew, Jie Sun, Gordon Haller