Patents by Inventor Gottfried Beer

Gottfried Beer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150054166
    Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 26, 2015
    Inventors: Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Publication number: 20150024591
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 22, 2015
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Patent number: 8912638
    Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Gottfried Beer
  • Patent number: 8890284
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 8889548
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Publication number: 20140332936
    Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 13, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Ulrich Wachter, Daniel Kehrer
  • Patent number: 8872315
    Abstract: A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Joachim Mahler, Ivan Nikitin, Gottfried Beer
  • Patent number: 8866292
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
  • Publication number: 20140310671
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Br├╝ckl, Rainer Leuschner
  • Publication number: 20140284624
    Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 25, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Juergen Hoegerl, Thilo Stolze
  • Publication number: 20140239438
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20140206109
    Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Peter Ossimitz, Matthias von Daak, Gottfried Beer
  • Patent number: 8786085
    Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joern Plagmann, Gottfried Beer
  • Patent number: 8779583
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Klaus Pressel, Gottfried Beer
  • Patent number: 8759207
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Mathias Vaupel, Rainer Steiner, Werner Robl, Jens Pohl, Joem Plagmann, Gottfried Beer
  • Patent number: 8728869
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 20, 2014
    Assignee: Intel Corporation
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Publication number: 20140127859
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Application
    Filed: January 14, 2014
    Publication date: May 8, 2014
    Applicant: Intel Mobile Communications GmbH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Publication number: 20140110858
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Walter Hartner
  • Publication number: 20140110840
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi