Abstract: Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract: A method for forming devices in an oxide layer over a substrate, wherein a metal containing layer forms at least either an etch stop layer below the oxide layer or a patterned mask above the oxide layer, wherein a patterned organic mask is above the oxide layer is provided. The substrate is placed in a plasma processing chamber. The oxide layer is etched through the patterned organic mask, wherein metal residue from the metal containing layer forms metal residue on sidewalls of the oxide layer. The patterned organic mask is stripped. The metal residue is cleaned by the steps comprising providing a cleaning gas comprising BCl3 and forming a plasma from the cleaning gas. The substrate is removed from the plasma processing chamber.

Abstract: An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.

Abstract: A method for etching a dielectric layer disposed below a patterned organic mask with features, with hardmasks at bottoms of some of the organic mask features is provided. An etch gas is provided. The etch gas is formed into a plasma. A bias RF with a frequency between 2 and 60 MHz is provided that provides pulsed bias with a pulse frequency between 10 Hz and 1 kHz wherein the pulsed bias selectively deposits on top of the organic mask with respect to the dielectric layer.

Abstract: A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H2. A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.

Abstract: A method for etching with CD reduction, an etch layer disposed below a silicon containing mask layer under a patterned organic mask with features with a first CD. Features are opened in the silicon containing mask layer using the patterned organic mask, comprising providing an opening gas with an etchant component and polymerizing component, forming the opening gas into a plasma, and providing a pulsed bias with a pulse frequency between 10 Hz and 1 kHz, which etches features through the silicon containing mask layer with a second CD, which is less than half the first CD, forming a pattern in the silicon containing mask layer. The pattern of the silicon containing mask layer is transferred to the etch layer.

Abstract: A method for forming features through a photoresist mask into an underlying layer is provided. The photoresist mask has patterned mask features. The photoresist mask has patterned mask features. A treatment gas containing H2 and N2 is provided. A plasma is generated from the treatment gas, and the photoresist mask is exposed to the plasma. The treatment gas is stopped, and then the features are etched into the underlying layer through the plasma-treated photoresist mask.

Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.

Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.